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NXP expands industrial control series to support energy-efficient controls and appliances

February 22, 2011 // Paul Buckley

NXP expands industrial control series to support energy-efficient controls and appliances

NXP Semiconductors N.V. has unveiled its LPC1200 Industrial Control Series featuring the ARM Cortex-M0 processor which extends NXPs 32-bit ARM microcontroller continuum and targets a wide range of industrial applications in the areas of factory and home automation, such as white goods, motor control, power conversion and power supplies.


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The new device also expands NXPs Cortex-M0 microcontroller offering with a wide range of Flash memory sizes. LPC1200 customers can now choose the exact Flash memory size they need, ranging from 32 KB to 128 KB in increments of 8 KB.

The LPC1200 product platform is specifically designed with flexibility and customization in mind, making it particularly suitable for a wide variety of energy-efficient system and power management requirements. For example, in advanced washing machines, the LPC1200 can control the motor systems, handle the user interface, monitor system power consumption, and manage off-board communications in a simple, integrated and energy-efficient solution. Its high current GPIO can directly control TRIACs without the need for external transistors, further reducing footprint and costs.

Designed for smart appliances and white goods In tomorrows energy-efficient smart appliance designs, the CPU will not only have to manage the user interface and control, but will also increasingly be required to drive multiple motor systems, as well as continuously measure current and voltage to calculate active power with high accuracy. The LPC1200 series meets these demanding system requirements with its high score of over 45 in CoreMark CPU performance benchmark testing, equivalent to 1.51/MHz.

For high volume applications, the LPC1200 platform can provide rapid delivery of application-specific solutions (ASSP) for a wide range of industrial control requirements, through flexible interconnections between the interrupt controller, DMA sub system, on-chip peripherals and GPIO. By recognizing external and internal events and carrying out pre-defined tasks without CPU intervention, the CPU load is dramatically reduced, allowing the CPU to remain in power down longer.
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