Panel reveals concerns over 450-mm wafers
March 07, 2011 // Peter Clarke
Whether Europe should try to contribute to 450-mm wafer technology research and deployment was revealed as a source of tension amongst Europe's leading chip makers at the Industry Strategy Symposium held in Grenoble, France.
Many of the panelists seemed to suggest that spending European tax-payers' money on 450-mm wafer research was not in their interest and risked diminishing support for mixed-signal, RF, MEMS and other CMOS derivatives below critical levels.
Elsewhere at the conference general approval had been shown for the European Commission's new-found interest in advanced manufacturing. This has partly been driven by campaigning by SEMI Europe in 2008 through 2010 and the European Commission has recently commissioned a study on the desirability of 450-mm pilot line in Europe.
Hans-Jurgen Straub, CEO of mixed-signal foundry X-Fab (Erfurt, Germany), set the tone for the panel when he said Europe could not live by services and that somebody has to manufacture something here. "We should do everything we can to keep it [semiconductor manufacturing] in Europe. We all have the same opinion, but then what do we do?"
Panelist Rutger Wijburg, vice president of front-end operations for NXP Semiconductors BV (Eindhoven, The Nethelands) asked: "450-mm; is it a curse or a blessing?" He suggested that a transition to manufacturing on 450-mm wafer could result in the chip industry collapsing to just three manufacturers, one in microprocessors, one in foundry and one in memory. "That may not be a great step-forward for consumers."
Jean-Marc Chery, chief technology officer of STMicroelectronics, said there are many strategic decisions to be made before considering 450-mm wafers. ST has a research and pilot fab in nearby Crolles, which could be a candidate to run 450-mm wafers at some point. "Today the challenge is the next CMOS platform and do we want to compete in the mobile Internet. If 'yes' then down to 10-nm node 300-mm wafers are competitive. FinFET [fin-shaped transistors] or FDSOI [fully-depleted silicon-on-insulator] is the first challenge. Then the choice of lithography and lithography is half the capex. Before we go to 450-mm we have to answer these fundamental questions."All news
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