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Partitioning tool eases multi-FPGA-based prototyping

July 17, 2014 // Julien Happich

Partitioning tool eases multi-FPGA-based prototyping

Cadence Design Systems has added the Protium rapid prototyping platform to its System Development Suite, claiming a 4X increase in capacity versus the previous generation but more importantly, reducing prototype bring-up time by up to 70 percent versus competitive solutions.

“Typically with competing solutions, designers use the implementation tools that are offered by the FPGA vendors, but these tools are only good for designs that fit into one FPGA. So designers have to rewrite their RTL to map it across multiple FPGAs, they must also remodel their memory, and it can take them up to three months to bring up the FPGA prototype” told us Frank Schirrmeister, Group Director at Cadence Design Systems and responsible for product management of the Cadence System Development Suite.

“By adding a software platform that takes care of this automatically, we bring down the set up time to a few weeks”, he added.

Built using Xilinx Virtex-7 2000T FPGAs, the Protium platform is Cadence's second-generation FPGA prototyping platform for software development, it supports up to 100 million gates. Featuring Palladium flow compatibility is another key advantage of the tool, since according the company, 95% of emulation users are also using FPGA-based prototyping.

The Protium platform enables software development and throughput regressions supported by a fully automatic flow and the capability to execute user-driven performance optimizations. It also provides automated memory compilation, external bulk memory support, and RTL name preservation throughout the flow, which minimizes the tedious and error-prone manual FPGA bring-up steps.

Using the same bring-up flow for Palladium emulation and Protium rapid prototyping, designers can switch seamlessly between the two execution engines, for example to benefit from the deeper debug features of the emulation platform.

Low-power analysis and verification is a key part of system and system-on-chip (SoC) signoff criteria. Addressing this, Cadence has expanded the Dynamic Power Analysis in the Palladium XP II platform beyond Common Power Format (CPF) support, adding verification and debug support for the IEEE 1801 standard.

The Cadence System Development Suite now offers an integrated and consistent low-power flow for engineers using either of the power standards across the Incisive formal and simulation and Palladium platforms, with common power plan and metrics, and integrated debug analysis.

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