Partitioning tool eases multi-FPGA-based prototyping
July 17, 2014 // Julien Happich
Cadence Design Systems has added the Protium rapid prototyping platform to its System Development Suite, claiming a 4X increase in capacity versus the previous generation but more importantly, reducing prototype bring-up time by up to 70 percent versus competitive solutions.
“Typically with competing solutions, designers use the implementation tools that are offered by the FPGA vendors, but these tools are only good for designs that fit into one FPGA. So designers have to rewrite their RTL to map it across multiple FPGAs, they must also remodel their memory, and it can take them up to three months to bring up the FPGA prototype” told us Frank Schirrmeister, Group Director at Cadence Design Systems and responsible for product management of the Cadence System Development Suite.
“By adding a software platform that takes care of this automatically, we bring down the set up time to a few weeks”, he added.
Built using Xilinx Virtex-7 2000T FPGAs, the Protium platform is Cadence's second-generation FPGA prototyping platform for software development, it supports up to 100 million gates. Featuring Palladium flow compatibility is another key advantage of the tool, since according the company, 95% of emulation users are also using FPGA-based prototyping.
The Protium platform enables software development and throughput regressions supported by a fully automatic flow and the capability to execute user-driven performance optimizations. It also provides automated memory compilation, external bulk memory support, and RTL name preservation throughout the flow, which minimizes the tedious and error-prone manual FPGA bring-up steps.
Using the same bring-up flow for Palladium emulation and Protium rapid prototyping, designers can switch seamlessly between the two execution engines, for example to benefit from the deeper debug features of the emulation platform.
Low-power analysis and verification is a key part of system and system-on-chip (SoC) signoff criteria. Addressing this, Cadence has expanded the Dynamic Power Analysis in the Palladium XP II platform beyond Common Power Format (CPF) support, adding verification and debug support for the IEEE 1801 standard.
The Cadence System Development Suite now offers an integrated and consistent low-power flow for engineers using either of the power standards across the Incisive formal and simulation and Palladium platforms, with common power plan and metrics, and integrated debug analysis.
Visit Cadence at www.cadence.com
Related news:All news
The engineering desk-to-bench ratio
November 21, 2014
Dennis Feucht discusses the right and wrong, senior and junior ways to organize the theoretical and practical work of an ...
Rohm's European Design Center in growth phase
Combo inertial sensor market on 19% CAGR, says Yole.
US, China pushing industrial chip market growth, says IHS
LA Auto Show: Hydrogen fuel cell drive is back
Opening up the IoT data flood gates
November 21, 2014
Only a few days after their LoRa long range communication demo at electronica, IBM and Semtech are making the LoRa MAC protocol ...
Polarizing filter reduces energy drain from smartphone displays
From warm to cool white: colour-temperature tunable LEDs
System provides high-volume solution for flexible OLED displays
- Halogen-free options and increased performance for terminal blocks
- Wireless Power User Guide
- Secure is the New Smart
- 5 Best Practices for Designing Flexible Test Stations
InterviewFreescale CEO: 'IoT isn't just buzz'
Coming after the solid third quarter results that produced higher operating margins and improving cash flow, Freescale Semiconductor's CEO Gregg Lowe had every reason to be chipper and lively when EE Times ...
Filter WizardCheck out the Filter Wizard Series of articles by Filter Guru Kendall Castor-Perry which provide invaluable practical Analog Design guidelines.
Linear video channel
READER OFFERRead more
This month, Cherry is giving away five of its Energy Harvesting Evaluation kits, worth over 266 Euros each, for EETimes Europe's readers to win. Cherry's energy harvesting technology benefit mostly applications where a complex wire assembly and/or batteries would be inappropriate.
The required RF-energy is created by the mechanical actuation of the switch and the data is transmitted...MORE INFO AND LAST MONTH' WINNERS...
December 15, 2011 | Texas instruments | 222901974
Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.
Most popular news
- Could magnesium battery innovation end lithium's dominance?
- From warm to cool white: colour-temperature tunable LEDs
- Li-Fi communication module wirelessly transfers data at 1-Gbps
- Supercapacitor innovation promises panel-powered cars in five years
- Rebranding the revolution: the future of IoT is embedded