Physically aware synthesis in RTL compiler delivers 15 percent improvement in power savings
November 21, 2013 // Paul Buckley
Cadence Design Systems, Inc. has introduced a new suite of physically aware RTL synthesis capabilities that deliver up to 15 percent improvement in power, performance and area.
The Encounter RTL Compiler version 13.1 offers the performance improvements compared with the most complex advanced node chip designs that face timing or congestion challenges.
The new capabilities are part of a production-ready physical synthesis engine that enables engineers to use physical aware techniques at the earliest phases of synthesis for better silicon results.
"While collaborating with Cadence on the development of several production designs, Fujitsu deployed RTL Compiler's next-generation physically aware RTL synthesis technologies on a 1 GHz, eight-CPU core design," said Satoru Yamaguchi, president and chief executive officer of Fujitsu Semiconductor America. "We were able to improve timing and area by more than 10 percent, allowing us to shrink the chips for our customer while demonstrating the benefit of this new synthesis solution."
As geometries shrink beyond 28 nm, changes in interconnect characteristics make it much more difficult to achieve optimal timing and closure. The new RTL Compiler capabilities let design teams address these challenges earlier in the design process so they can achieve faster timing closure, while improving performance, power and area.
The new RTL synthesis capabilities include physically aware structuring, mapping, multi-bit cell inferencing and design for test that offer significant benefits for Cadence customers. Physically aware structuring and mapping can improve performance by more than 10 percent and area by more than 15 percent on complex SoCs by considering pin and register placement when deciding which micro-architectures to synthesize to, and how to balance them. Physically aware multi-bit cell inferencing can lower power by more than 10 percent by merging single registers into multi-bit registers that share a clock.
"Cadence has re-architected RTL Compiler to weave physical awareness into stages of RTL synthesis that were traditionally logic only, allowing engineers to leverage floorplan and placement data as early as possible in the flow to ensure correlation with the Encounter Digital Implementation System," said Anirudh Devgan, senior vice president of the Digital and Signoff Group at Cadence. "Our investment continues in this area, with our customers citing benefits for timing, power, and area in a wide range of target applications and better out-of-box results reducing iterations."
More information about the RTL Compiler at www.cadence.com/news/RTL
Extensible CPU cores exploit IoT's vast potential
May 22, 2015
Cisco Systems has predicted that by 2020, there will be 50 billion “things” connected to the Internet up from 15 billion ...
Audi connects to Baidu, Huawei at CES Asia
New class of magnets attract energy harvesting attention
Sony raises image sensor capex...again
OneSpin Solutions takes formal verification to the App store
Why the speculations on Nokia’s map service HERE run hot
May 21, 2015
Nokia’s digital map service HERE is on the block – and a crowd of suitors are outbidding each other. But some remain at the ...
Flexible OLED display peels off the wall
Irish battery R&D facility targets advanced material development
Bosch adjusts course for future mobility requirements
- Integrating GPS into consumer products
- Controlling LED Lighting Using Triacs and Quadracs
- Automotive Designs Demand Low EMI Synchronous Buck Converters
- Smart Capacitive Design Tips
InterviewCEO interview: What's next after Tower's turn-around?
May 2015 marks the tenth anniversary of Russell Ellwanger taking over as CEO of speciality foundry Tower Semiconductor Ltd. (Migdael Haemek, Israel), which now trades as TowerJazz. And so EE Times Europe ...
Filter WizardCheck out the Filter Wizard Series of articles by Filter Guru Kendall Castor-Perry which provide invaluable practical Analog Design guidelines.
Linear video channel
READER OFFERRead more
In this month's reader offer, Analog Devices is giving away five Blackfin Low-Power Imaging Platform (BLIP) Development Systems (ADZS-BF707-BLIP2), worth 199 dollars each, for EETimes Europe's readers to win.
Targeting demanding ultra-low-power, real-time applications for image sensing and advanced audio, the development platform leverages the company’s ADSP-BF707BBCZ-4 Blackfin processor as...MORE INFO AND LAST MONTH' WINNERS...
December 15, 2011 | Texas instruments | 222901974
Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.