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Power integrity analysis engine delivers 10X faster performance

November 12, 2013 // Paul Buckley

Power integrity analysis engine delivers 10X faster performance

Cadence Design Systems, Inc. has introduced a power integrity analysis engine that uses massively distributed parallel execution to achieve a scalable performance gain up to 10X compared with competing products.


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The Voltus IC Power Integrity Solution, claims to deliver record performance and capacity power analysis to meet the needs of next-generation chip design. Cadence claims that Voltus is the industrys first power integrity tool integrated with static timing analysis.

Voltus draws on new technology as well as integration with Cadence IC, package, PCB and system tools to enable design teams to better manage power issues throughout the product development cycle and achieve faster design closure.

The Voltus solution is aimed at speeding design signoff and closure and follows Cadence's release in May 2013 of the company's Tempus Timing Signoff Solution.

Voltus solution enables designers to shrink the critical power signoff closure and analysis phase to a minimum.

Voltus uses a hierarchical architecture that is capable of supporting large designs, and when coupled with the parallel execution, scales to multiple CPU cores and servers, enabling the analysis of designs of up to a billion instances. SPICE-accurate solver technology provides the most accurate power signoff results.

The Voltus analysis engine enables power calculation across the chip and addresses leakage, switching and internal power issues. The tool is also capable of carrying out power integrity analysis on the power grid by implementing IR-drop and electro migration checks.

Physically-aware power integrity optimization, such as early rail analysis, de-coupling cap and power gating switches, helps improve physical implementation quality and speeds up design closure. The tool is capable of focusing on power gating switch issues to provide designers with early power grid analysis during the floorplanning phase.

The Voltus IC Power Integrity Solution claims to provide even greater benefits when integrated with other Cadence tools. When used with the Tempus Timing Signoff Solution Cadence can offer the industrys first unified electrical signoff solution for faster, converged timing and power signoff.

Many of the capabilities of Voltus are geared to tackle the design challenges posed by the increasing low power requirements of mobile devices which need to
extend battery life and increase device reliability. Cadence points out that design complexity increases when low power ICs are involved because of the advanced design techniques being used plus the increasing level of IP content and functionality is creating tighter design margins.

Power integrity is becoming increasingly critical for successful design signoff and because it often occurs late in the design cycle there is a major impact on timing and physical design closure. Cadence believes that many power solutions have not kept pace with a designers requirements and the time needed for power analysis is increasing owing to the growth in design complexity and size of the ICs which are imposing more complex analysis demands. The company says that current solutions often do not consider the impact of power on timing closure of projects. There are also fresh challenges being raised by the advent of 3DIC technology. Many of these challenges focus on thermal breakdown issues and call for complete power integrity analysis from chip to package to system.

By combining Voltus with Cadence's Encounter Digital Implementation System and Allegro Sigrity Power Integrity tools allows designers to implement a comprehensive power integrity solution encompassing chip, package and PCB.

When integrated with the Virtuoso Power System software Voltus enables analysis of custom/analog IP in an analog mixed-signal SoC design.

Accurate IC chip power integrity analysis, driven by real-world power stimulus is also possible when Voltus is used with Palladium Dynamic Power Analysis functionality.

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