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Programmable SPI-4.2 core launched as IP

September 21, 2010 // Phil Ling

A full rate SPI-4.2 solution based on the LatticeECP3 FPGA fabric has been announced with immediate availability.† The Lattice-developed soft Intellectual Property (IP) core is fully compliant with the Optical Internetworking Forum's (OIF) System Packet Interface Level 4 (SPI-4) Phase 2 Revision 1 Standard. The SPI-4.2 IP core is available now, list price of $3,000 and can be ordered through Lattice sales.

Said to be a popular parallel interface found in telecom/datacom applications at 10Gbps rates and below, the solution operates at the full 10Gbps line rate, which Lattice claims is made possible by its sysI/O interface structure. It contains pre-engineered elements designed to support the implementation of very fast, source synchronous interfaces such as high speed DDR2 and DDR3 memory interfaces and SPI-4.2. 

Lattice's SPI-4.2 solution is supported by its IPexpress FPGA design tool module.  Included as a standard feature in the Lattice Diamond design tool suite, the IPexpress module significantly reduces design time by allowing IP parameterization and timing analysis on the designer's desktop.  This allows users to customize Lattice's extensive library of IP functions for their unique applications, integrate them with their proprietary FPGA logic designs and evaluate the overall device operation via simulation and timing analysis prior to making any IP purchase commitments.     The new SPI-4.2 soft IP core requires about 4000 FPGA look-up tables (LUTs) in 128-bit mode for a full 256-channel static mode core.  It therefore can be implemented along with other user logic in all LatticeECP3 family members, from the LatticeECP3-17 device through the largest member of the family, the LatticeECP3-150 device. 

The SPI-4.2 core operates at interface speeds of up to 11.2Gbps, while fulfilling all requirements of the SPI-4.2 interface protocol, including support for up to 256 logic channels, calendars, transmit and receive status, programmable burst size and DIP4 error checking.    

For more information on the IP core visit

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