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Second generation 65-GSa/s 8-bit ADC technology focuses on 100G optical transport

September 13, 2010 // Paul Buckley

Second generation 65-GSa/s 8-bit ADC technology focuses on 100G optical transport

Fujitsu Semiconductor Europe announces its second generation 8-bit CHArge-mode Interleaved Sampler (CHAIS) ADC for optical transport designs based on coherent detection.  The new generation supports data rates from 55 to 65 GSa/s and is based on the same ADC architecture as Fujitsu's 56 GSa/s CHAIS ADC in 65 nm.


The device offers the ultra-fast sampling rates, wideband input, low noise and high resolution required for long-haul links with data rates of 100Gbps and higher over a single wavelength.     

Implemented in a high-performance 0.9 V 40 nm CMOS technology, the 65 GSa/s CHAIS ADC surpasses even the low power performance of the first generation and will support higher FEC overheads for longer reach. The fundamentals of the CHAIS architecture allow for scalability to even higher sampling rates for future transport data rates (400 Gbps/1Tbps) and power dissipation that scales with smaller process feature size. Typical power dissipation for a single CHAIS ADC channel in 40 nm is only 1.2 W, down 50% from the power per channel in 65 nm.   

Fujitsu's 4-channel CMOS design allows for more efficient integration with coherent receiver digital cores, typically comprising tens of millions of logic gates and a multi-terabit data transfer rate across the interface between core and ADCs. For the design of single-die transceiver SoCs in 40 nm, the Fujitsu IP offering includes high speed 11Gbps SerDes, supporting a range of protocols and data rates, and will also include a complementary high speed 55 to 65 GSa/s 8-bit DAC.     

Availability     

Fujitsu Semiconductor Europe will be demonstrating the 65GSa/s CHAIS performance at the European Conference on Optical Communications (ECOC) in Turin, Italy later this month.  As with the previous generation CHAIS ADC technology, a development kit for the 65GSa/s ADC will be available in January 2011 for customers to evaluate their modulation and FEC algorithm performance using silicon based on field-proven architectures.     

More information about the Fujitsu Semiconductor Europe 8-bit (CHAIS) ADC at   
http://emea.fujitsu.com/chais

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