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Sematech, SRC and SIA plan 3-D chip infrastructure

December 09, 2010 // Jean-Pierre Joosting

Sematech, SRC and SIA plan 3-D chip infrastructure

Sematech, SIA, and SRC have announced a program to drive industry standardization and the technical specifications for heterogeneous 3-D integration.

Sematech is the international consortium of leading semiconductor manufacturers, while the Semiconductor Research Consorium is active in collaborative research for the semiconductor industry. The Semicondcutor Industry Association is the leading representative of the semicondcutor industry's main players.

The new program will be administered by Sematech’s 3-D Interconnect program in partnership with SRC and be based at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany

The program aims to establish the infrastructure necessary for the industry to leverage 3-D packaging technology for new applications and will focus on establishing standards in inspection, metrology, microbumping, bonding and thin wafer and die handling.

To achieve this Sematech will partner with SRC to enable select university research projects.

"The 3-D Enablement program has been established to bring down the barriers to integrating chips from different suppliers for adoption of 3-D technologies in high volume manufacturing," said Dan Armbrust, president and CEO of Sematech, in a statement.

While research on 3-D technologies has been ongoing for many years as witnessed by technical papers delivered at esteemed venues such as the International Electron Devices Meeting and the International Solid State Circuits Conference, 3-D has not yet made it to mainstream production due to lack of uniform standards and a limited understanding of key manufacturing parameters.

The program will address industry infrastructure gaps in phases. First efforts will focus on developing the necessary standards and technical specifications, followed by planning activities to identify the key areas for developing design tools to support 3-D chip design.

Designed to meet the needs of diverse business models, the 3-D Enablement program is open to international fabless, fab-lite and Integrated Device Manufacturers (IDM), outsourced assembly and test (OSAT) suppliers, and tool vendors.

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