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Silicon-on-insulator at STM and IBM closing gap with Intel

April 17, 2012 // R. Colin Johnson

Silicon-on-insulator at STM and IBM closing gap with Intel

Silicon wafer maker Soitec S.A. claims that chip makers can sidestep years of development work needed to perfect fully-depleted (FD) silicon transistors by switching to its silicon-on-insulator (SOI) wafers, a ploy that has already convinced STMicroelectronics NV, ST-Ericsson and IBM Corp., to give it a try.

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"Fully depleted transistor channels are quickly becoming a necessity for semiconductor manufacturers moving below the 32-nanometer node," said Steve Longoria, senior vice president of global strategic business development at Soitec. "IBM is going to SOI wafers for its FinFETs at the 14-nanometer node, and STMicroelectronics and ST-Ericsson are working with us to develop 2D fully-depleted transistors for their next-generation mobile processors at 28-nanometer."

One of the biggest problems facing continued scaling of semiconductors below the 32-nanometer node is non-uniformities of dopants in the nanoscale-thin transistor-channel layer. To solve that problem, the industry is going to undoped channels for FD transistors. Intel has gone to great lengths to design FD undoped channels for its tri-gate FinFET transistor using standard bulk silicon wafers, which as a result requires sidewall implant doping to isolate the channel and prevent excess leakage current into the substrate.

Soitec has two flavors of its SOI wafers, one for traditional planar transistors that offers and ultra-thin top silicon layer with tollerances of plus or minus just five angstroms, for the FD transistor channels, atop an ultra-thin buried oxide layer that prevents leakage into the substrate without the extra process steps that Intel uses for its bulk-silicon process.

The second SOI wafer from Soitec is for 3-D FinFET transistors, such as those IBM has announced it will use at the 14-nm node. The 3-D SOI wafer has thicker top silicon layers for the tall 3-D fins and a thicker buried oxide layer to accommodate the higher fields produced by the multiple metal gates.

Both the 2-D planar and 3-D SOI wafers cost about four-times more than bulk siliconaccounting for Intel's reluctance to use them for its tri-gate FinFET process. But Soitec claims that the time gained in FD transistor development plus the fewer processing steps required when fabricating FD channels with sidewall implantation, more than makes up for the high price of the wafers.

"Our wafers cost about $500 wafer compared to $120 for bulk silicon," said Longoria. "But their price is recouped from process simplifications to give a three-to-10 times overall cost reduction."

Soitec claims FD transistors built using its SOI wafers provide 40 percent better performance, or because of the drastic cut in leakage current supplied by the buried oxide layer, can alternatively provide 40 percent lower power when operated at current performance levels. Soitec also claims to be working with both IBM and ARM to create a specification for SOI wafers for taking their traditional planar transistors to undoped FD channels, which can nix problems with short-channel effects where closely spaced source and drain electrodes start leaking through a bulk-silicon substrate.


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