ST, Intel delayed phase-change memory to make improvements
February 12, 2008 //
Researchers from Intel and STMicroelectronics could have produced samples of 128-Mbit phase-change memories in 90-nm process technology as early as June 2007 but opted instead to take time to improve the memory, according to Paolo Cappelletti, group vice president for advanced technology development at ST's flash memory group.
LONDON Researchers from Intel and STMicroelectronics could have produced samples of 128-Mbit phase-change memories in 90-nm process technology as early as June 2007 but opted instead to take time to improve the memory, according to Paolo Cappelletti, group vice president for advanced technology development at ST's flash memory group.
In March 2007 Intel organized a teleconference in which Ed Doller, then chief technology officer of the flash memory group at Intel, told listeners that Intel was preparing to sample a 90-nm 128-Mbit phase change memory to customers in the first half of 2007. Doller said at the time that he was hopeful the memory would go into volume production by the end of the 2007.
The phase-change memory is based on a thermally-induced reversible change in a chalcogenide material - between an amorphous and crystalline state. The 128-Mbit device has been designed as a pin-compatible NOR replacement that provides fast read and write speeds at lower power than conventional flash, and allows for the bit alterability normally seen in RAM.
Capelletti told EE Times that the 90-nm nonvolatile phase-change memory was delayed from that original prediction to help build a better foundation for a memory product at a more advanced manufacturing node.
During the first half of 2007 engineers working on the follow-on to the 90-nm phase-change memory at an ST pilot line in Agrate, Italy, made some changes to the memory cell to improve integration, said Cappelletti. "We saved one critical mask, made the memory cell more scalable and changed the electrical distribution across the array."
"We were not yet in production so we decided to reproduce these changes in 90-nm," said Cappelletti. He added that the decision was done to allow an easier transition from the 128-Mbit 90-nm memory to the next-generation. Cappelletti said he could not say whether that would be implemented in a 65-nm process.
"We were able to produce the 90-nm sample in Q4 2007. The shipment happened in Q1 because we wanted to tie three events together * the delivery of samples; the ISSCC paper on multilevel cell PCM and the demonstration in Barcelona," Cappelletti said.
The reference to Barcelona is believed to be a demonstration of the use of phase-change memory as a replacement for NOR flash memory within a mobile phone.
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