ST, ST-Ericsson commit to SOI, says Soitec
March 13, 2012 // Peter Clarke
Soitec SA, a supplier of silicon-on-insulator (SOI) wafers, has announced that mobile chip joint venture ST-Ericsson NV has selected planar fully depleted SOI (FD-SOI) technology for use with future mobile chips.
It is thought that NovaThor family has been developed using bulk CMOS at least until 28-nm CMOS. So it appears that Soitec is announcing the use of FD-SOI for devices designed to be implemented in processes below 28-nm.
"Next-generation mobile consumer devices will need to deliver an even better user experience and higher performance without sacrificing battery life," said Louis Tannyeres, chief chip architect, ST-Ericsson (Geneva, Switzerland), in a statement issued by Soitec. "Together with innovations in overall platform system design, advances in process technology are key to delivering next-level performance and higher power efficiency. The results of our work with STMicroelectronics on FD-SOI have demonstrated that this technology is able to deliver these benefits in a cost-effective manner, while allowing us to differentiate our solutions."
"FD provides a low-risk option for semiconductor companies such as ST-Ericsson that are seeking to take advantage of the benefits of a fully depleted transistor architecture while leveraging existing design and manufacturing capabilities," said Paul Boudre, chief operating officer of Soitec, in the same statment. "This announcement represents the industry's first step toward fully depleted planar CMOS technology, years ahead of when alternative processes will be available from foundries. We are positioned to provide the volume of qualified wafer manufacturing required to enable the industry to speed the adoption of planar fully depleted technology into mainstream mobile applications."All news
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