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Startup slashes SRAM power with standard logic process

March 04, 2014 // Nick Flaherty

Startup slashes SRAM power with standard logic process

A UK startup has developed an entirely new way of building static memory on a standard logic process that cuts the power in half without paying a penalty in area or speed.


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"Fundamentally memory has some real problems everyone does it the same way," said Mark de Souza, chief executive at Silicon Basis in Bristol and formerly at memory IP supplier Virage Logic. "They all take the TSMC arrays and put them together."
Silicon Basis sees two key advantages for its technology it can save up to 50% of the power consumption and it can go below the bit cell voltage of the foundry memories. This allows the memories to be powered by the same voltage source as the logic and so eliminates the need for a second DC-DC converter. It also makes the technology foundry independent and scalable to new technologies such as FinFet, says de Souza. The company, based in the SETsquared center in Brunel's EngineShed in Bristol, has produced all the models needed and is now working on 28nm silicon to prove the implementation.
"We use our own bit cell so we are not restricted to the foundry's Vmin which is a huge advantage," said de Souza, (pictured above right). "Dropping the voltage makes a huge difference."
All of this comes from a new way of looking at the design of the cell which is currently being patented.
"No one has seen this way of designing SRAM before," he said. "We are talking to the experts in memory design and no one has seen this way of putting memory together. Its all using standard rules and standard CMOS. Its an architectural difference that means we dont need to use sense amps and because we are using logic rules we can go down to the logic voltage floor and possibly below that."
"Our cell size is about the same as the high speed cell from the foundry," said Rob Beat, founder and chief technology officer of Silicon Basis and designer of the new cell. "There's a compromise on area in the array but because the periphery is more efficient we are competitive in area especially on the smaller RAMs."
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