Synopsys extends HAPS debug visibility by 100X in FPGA-based prototypes
April 26, 2012 // Julien Happich
Synopsys has released a new Deep Trace Debug feature for users of its HAPS FPGA based prototyping systems. With HAPS Deep Trace Debug, prototypers can take advantage of approximately 100 times more signal storage capacity than the traditional memory storage employed by on chip FPGA logic debuggers.
The new Deep Trace Debug feature enhances both capacity and fault isolation capabilities while freeing up the on chip FPGA memory required for validating complex system on chip (SoC) designs. “The Qualcomm Atheros' Wi-Fi/Bluetooth combo products use leading edge Wi-Fi standards to achieve gigabit per second throughput, requiring advanced hardware software validation techniques like those available in Synopsys’ HAPS systems,” said Manoj Unnikrishnan, director of engineering at Qualcomm Atheros. “Our traditional approach required multiple runs with a lot of trial and error. The high capacity sample storage available with HAPS Deep Trace Debug allows us to quickly identify bugs and speed full system validation. In addition, HAPS Deep Trace Debug will help us improve state machine coverage, prototyping coverage, and test pattern generation.”
Confirming correct functionality of high speed interface designs often requires sampling at dozens of frequencies for several milliseconds at a time. Traditionally, designers have had to make a choice between capturing long signal trace histories that consume extensive FPGA memory resources or saving FPGA memory resources but losing detailed visibility into signal trace history. By pairing the Synopsys Identify Intelligent Integrated Circuit Emulator (IICE) with a HAPS Deep Trace Debug SRAM daughter board, HAPS Deep Trace Debug allows many unique signal probes with complex triggers to be recorded and provides deeper memory to store extensive state history as the system executes. The SRAM daughter board also frees up the FPGA’s on chip RAM for prototyping an SoC design’s memory blocks.
Visit Synopsys at www.synopsys.comAll news
Ultrasounds and plastic in place of complex electronics
May 06, 2015
In a joint project from Carnegie Mellon University HCI Institute and Disney Research, researchers have demonstrated the use ...
Infineon seeks buyer for Welsh wafer fab
ST falls to fourth in 2014 sensor sales ranking
Six Android apps for analog engineers
OmniVision agrees to become Chinese
NXP / Freescale: A chipmaker takes shape
May 06, 2015
After the upcoming merger of NXP and Freescale, how will the resulting company look like? At the recent CDN Live Cadence ...
Idea Challenge contest calls for digital startups
Hybrid perovskite FETs in the lab
Centimeter-accurate GPS receiver to boost digital mapping
- Automotive Designs Demand Low EMI Synchronous Buck Converters
- Smart Capacitive Design Tips
- Wireless MCUs and IoT
- Battery Management System Tutorial
InterviewInfineon: CAN FD success goes at the expense of FlexRay
The faster version of the venerable CAN bus, CAN FD is currently taking off at several carmakers. Infineon's Thomas Böhm, Head of Body / Automotive, believes this could well go at the expense of FlexRay. ...
Filter WizardCheck out the Filter Wizard Series of articles by Filter Guru Kendall Castor-Perry which provide invaluable practical Analog Design guidelines.
Linear video channel
READER OFFERRead more
In this month's reader offer, Analog Devices is giving away five Blackfin Low-Power Imaging Platform (BLIP) Development Systems (ADZS-BF707-BLIP2), worth 199 dollars each, for EETimes Europe's readers to win.
Targeting demanding ultra-low-power, real-time applications for image sensing and advanced audio, the development platform leverages the company’s ADSP-BF707BBCZ-4 Blackfin processor as...MORE INFO AND LAST MONTH' WINNERS...
December 15, 2011 | Texas instruments | 222901974
Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.