Synopsys, Varian to develop TCAD models for logic, memory devices
February 11, 2011 // Anne-Françoise PELE
Synopsys and Varian Semiconductor Equipment Associates have joined forces to develop Technology CAD (TCAD) models that address cryogenic ion implantation for leakage reduction of leading-edge logic and memory devices.
Synopsys and Varian claimed that the TCAD Sentaurus models derived from their collaborative work will speed up process development of advanced CMOS and memory technologies and reduce process development cost and time-to-market.
As part of this collaboration, Synopsys said it will use experimental data from Varian's cryogenic implant process to develop and calibrate models for its TCAD Sentaurus tools.
"Today semiconductor manufacturers face tremendous challenges in improving device performance, achieving high product yield, reducing process R&D costs and meeting time-to-market targets. Therefore, it is increasingly critical for simulation to support novel process techniques to reduce technology development time and cost," stated Dr Yuri Erokhin, senior director for strategic technologies at Varian.
Erokhin continued: "Cryogenic ion implant has been proven to significantly improve transistor performance and is a key enabler in the manufacture of advanced devices. This collaboration with Synopsys will enable our mutual customers to explore and optimize the cryogenic implant process with simulation, reducing time-to-market."
Back in 2005, Synopsys announced the addition of the Varian's ion implantation process data to its Sentaurus Calibration Library.
By incorporating the Varian Semiconductor data, Synopsys then said it had increased the predictability and accuracy of TCAD process simulation for advanced ultra- shallow junction (USJ) CMOS technology, allowing semiconductor manufacturers to reduce the overall cost and time for product development.
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