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Tackling the European challenges in verification

August 16, 2012 // Nick Flaherty

Tackling the European challenges in verification

EETimes Europe asked Mike Bartley of leading verification house TVS to look at how European companies see the challenges and possible solutions.


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The major silicon companies in Europe see the rise in design complexity as a major verification challenge but see different methods of solving this. ARM, ST, Infineon and Ericsson each identified their top verification challenges at the European-wide VerificationFutures conference. With VerificationFutures running in UK, Germany and France in November 2012 Mike Bartley sees the challenges and possible solutions ahead.
Clemens Muller of Infineon saw complexity in the whole system, both the hardware and the software. He wanted tools to help master that combined complexity with true hardware-software co-verification. Co-simulation is obviously a start but engineers require a combined hardware-software view of the simulation. Software engineers have a completely different view of the system and do not want to debug with waveforms. All four companies also pointed out that the solution starts earlier in the design process with ESL (Electronic System Level) design usually with SystemC. The TLM2.0 standard should enable users to more easily port their test benches seamlessly between SystemC and RTL. For example, Mentor Graphics highlighted their release of UVM Connect at DAC. This is a new open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog.
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