NICE, France — Tanner EDA has added hierarchical 3D resistance and capacitance (RC) extraction capabilities to its L-Edit chip layout tool for analogue and mixed-signal design.

The HiPer-PX tool accurate modelling of parasitics occurring both across metal layers and between the metal layers and the chip substrate. It can also extract the device substrate resistance, which can have an effect on crosstalk at the sub-micron level.

The tool reduces design errors and shortens the design verification process, particularly for deep sub-micron technologies where interconnect delays start to play a dominant role and second-order effects such as cross coupling become significant.

HiPer-PX is integrated within L-Edit and the extraction process is based on proven field solver technology. The tool extracts the resistance and capacitance of interconnects and devices, highlighting any potential crosstalk and timing delays in the design.

Both 2D and 3D electromagnetic field analysis techniques accurately and efficiently extract RC values from the layout and detailed simulation in SPICE determines time delays and signal integrity effects. The extraction tool determines problem nets based on criteria that are critical to design performance and provides batch mode processing for easily checking multiple blocks.

The L-Edit layout editor has an intuitive interface which increases drawing speed through the use of object snapping, one-click horizontal or vertical alignment, and base points. The tool can perform complex Boolean and derived layer operations with arbitrary polygonal curves and shapes and it uses external GDSII cell libraries for a smooth design flow.