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Toshiba licenses processor architecture, multiprocessor tools from IMEC

October 13, 2008 //

Research institute IMEC, announced that Japanese chipmaker Toshiba Corp. has licensed IMEC technology to help it design power-efficient single- and multiprocessor wireless baseband system chips with gigabit per second download capabilities.


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LEUVEN, Belgium Research institute IMEC, announced that Japanese chipmaker Toshiba Corp. has licensed IMEC technology to help it design power-efficient single- and multiprocessor wireless baseband system chips with gigabit per second download capabilities.

The agreement covers IMEC's ADRES reconfigurable processor template, the DRESC compiler that goes with ADRES and the MPSoC (multi-processor system-on-chip) suite of design tools. Toshiba has made a one-time payment to IMEC for the license to use the intellectual property in a non-exclusive deal. IMEC will cooperate to help Toshiba to develop processors and tools that enable gigabit per second demodulation.

ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a processor architecture designed for wireless and multimedia processing in single- and multiprocessor systems. ADRES processors are suited for future mobile terminals, such as software-defined radios.

The processor has a coarse-grained VLIW (very long instruction word) multiprocessor architecture and has been used as the basis for the development of a reconfigurable processor for video decoding that has achieved power efficiencies up to 12 times higher than C-programmed processors, IMEC has claimed.

It has the ability to adapt between a one dimensional array of function units operating in VLIW mode and a two-dimensional array of processing elements while using the same C compiler. This ability to adapt dynamically is way to minimize the appearance of "no-ops" in functional units which is a source of power consumption problems for static VLIW machines. The distributed memory architecture is also an advantage according to IMEC experts. The processor was developed to support MPEG-2, MPEG-4 and H.264/AVC video decoding at resolutions ranging from QVGA up to D1, but as multiple ADRES processors can be put down on a single die, and the internal architecture is scalable it can be used for higher bandwidth applications.

Through an XML template, designers can create the ADRES processor instance that is best suited for their applications. And applications for an ADRES processor can be completely programmed in C and compiled with the DRESC compiler, included in the license.

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