LONDON — The prototype of a novel polymorphous general purpose microprocessor architecture being developed and built in the Department of Computer Sciences at The University of Texas at Austin, is due to be unveiled on Monday (April 30) at a public presentation on the university campus.

The TRIPS (The Tera-op, Reliable, Intelligently adaptive Processing System) processor has been in development for more than seven years and is being billed as an architecture that will be able to scale until the end of the silicon era. Sponsors of the technology include IBM, Intel and Sun Microsystems Inc.

The research team, led by Professors Doug Burger, Stephen Keckler and Kathryn McKinley, has been working on the design of the processor, a cross-platform compiler and an instruction set architecture. The goal has been to produce a scalable architecture that can accelerate industrial, consumer, embedded and scientific workloads, reaching trillions of calculations per second on a single chip.

While the development of the TRIPS processor has largely been an academic exercise over the last several years in the theory of parallel and multiprocessing, the fact that commercial processors have recently gone "multicore" is giving TRIPS added resonance and traction right now.

The TRIPS architecture, based on Explicit Data Graph Execution (EDGE), can produce improved single-thread performance at — better power efficiencies — than conventional designs, the development team claims. The goal is to accelerate industrial, consumer, embedded, and scientific workloads, reaching trillions of calculations per second on a single chip.

Most current processors were originally designed as uniprocessors. Performance can be improved by adding more processors, but this often puts a burden of parallelization on software writers — a burden they are frequently not prepared to shoulder. It is also hard to overcome inefficiencies of intra-processor communications as the number of processors is increased. The most successful examples of multiprocessor designs have been where the processor is application specific and a uniprocessor programming model can be presented to software writers through the use of in intermediate hardware abstraction layer.

The TRIPS prototype processor is composed of many copies of a small number of replicated tiles. It contains two processing cores, each of which can issue 16 operations per cycle with up to 1,024 instructions in flight simultaneously. The prototype is the first on a roadmap that the research team claimed would lead to more powerful flexible processors implemented in nanoscale technologies.

Back in September 2003, the University of Texas team said it expected to have operational prototypes by the end of 2005 with each prototype including four Trips processors, each containing 16 execution units laid out in a 4 by 4 grid. At that time the group developing TRIPS was looking for commercial partners willing to bring the technology to market.

The TRIPS team partnered with IBM Microelectronics for ASIC physical design, including placement, routing, and fabrication. First silicon was delivered on September 27, 2006. The TRIPS prototype chip is a 170 million transistor custom ASIC designed in a 130-nm technology that runs at a clock frequency of 366-MHz and achieves 12 GFlops.

Funding for the TRIPS project is provided by the Defense Advanced Research Projects Agency.

The TRIPS processor executes code generated by a custom compiler from sequential C or Fortran. The compiler includes algorithms designed to create large blocks that can execute atomically, according to the EDGE specifications. In addition, the compiler includes a spatial instruction scheduler which places instructions to be executed on the distributed execution substrate such that communication latency and contention among the tiles are minimized.

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