Using compression to meet pin-limited test requirements
January 21, 2010 //
Timely delivery of highly reliable semiconductor products to market is essential to success in todayÕs competitive business environment. As if following through on this objective were not already challenging enough, companies today are facing yet another challenge: fewer pins available for digital testing.
Timely delivery of highly reliable semiconductor products to market is essential to success in today's competitive business environment.
As if following through on this objective were not already challenging enough, companies today are facing yet another challenge: fewer pins available for digital testing.
This article looks at the potential impact that availability of fewer test pins has on test quality and cost, and how one company, Wolfson Microelectronics, is using new technology in Synopsys' DFTMAX compression to simplify the task of pin-limited testing.
Growing pressure for scan compression
Over the past decade, advances in design automation technology have led to the widespread adoption of on-chip test data compression as an efficient means to improve test quality and lower the costs of testing digital integrated circuits (ICs).
Scan compression  reduces test data volume compared with conventional scan testing, freeing up automatic test equipment (ATE) memory for additional test patterns that improve defect screening.
It is no coincidence that the "mainstreaming of compression technology has coincided with the widespread use of pattern-rich deep-submicron (DSM) tests that identify subtle defects in nanometer-scale manufacturing processes.
Moreover, scan compression significantly reduces the time needed to test a device, which can dramatically lower the cost of high-volume production testing.
Compression requirements, however, continue to evolve across the semiconductor industry. Increased focus on packaging costs and tighter form factors for portable applications are leading to more stringent packaging constraints that limit the number of pins available for scan compression.
In many cases there are a sufficient number of pins available at wafer probe, but few pins remain accessible for subsequent testing of packaged parts. In an effort to further reduce costs at the tester, designers are increasingly employing compression with multi-site testing, a technique that tests multiple die simultaneously.
The more die tested in parallel, the shorter the test time and the greater the potential cost savings; however, because the tester channels are divided among multiple die, compression must accommodate fewer scan inputs and outputs.
In addition, to better manage the complexity of large systems-on-chip, designers are deploying core-based methodologies wherein multiple cores are synthesized and verified independently prior to integration at the chip-level. In this arrangement, each core includes its own embedded compressor/decompressor (CODEC).
Because many such cores are contained in a design, each CODEC may have access to only a few chip-level test pins for compression.
These and other emerging design-for-test (DFT) methodologies such as 3D IC stacking in a single systems-in-a-package are driving the need for scan compression to deliver high test data volume reduction (TDVR) and test application time reduction (TATR) for pin-limited testing.
As the design automation industry responds to this demand, companies such as Wolfson Microelectronics are now benefiting from deploying scan compression that delivers high quality-of-results using few test pins.
Less accessible pins
Wolfson Microelectronics' designs are comprised mostly of analogue circuits that connect to analogue pins. Only a few digital pins are needed for the digital portion of a design, and these must be used for all the digital testing.
The company makes use of high-end mixed-signal testers, which often have less memory available per pin than low-cost digital testers. Adding more pins dedicated for testing is not a viable option as this would increase die and packaging costs.
Two years ago, the complexity of Wolfson's digital circuits had increased to the extent that designers began using Synopsys' DFTMAX compression for TDVR to ensure all the stuck-at patterns for a design could be loaded into tester memory.
Widely deployed throughout the semiconductor industry and tightly linked with TetraMAX ATPG (automatic test pattern generation), DFTMAX compression uses adaptive scan technology to reduce test data volume and test application time in equal proportions.
Wolfson's designs at that time typically included 5 or 6 digital pins, so only a relatively small amount of compression was needed. For larger designs requiring higher TDVR, the scan compression patterns were supplemented with "top-off patterns from standard (reconfigured) scan mode to improve test coverage.
To-date, Wolfson has released more than two dozen designs to production using the Synopsys test solution. Over the past year, the digital content of Wolfson's mixed-signal ICs has increased while the number of digital pins has decreased.
To realize the full potential for high test quality at low cost for Wolfson's latest designs, designers needed enhanced compression capability for pin-limited testing that not only helped them meet their TDVR requirements without the need to generate top-off patterns, but also allowed them to benefit from cost savings due to further reductions in test application time.
To deliver both high TDVR and high TATR with few test data pins, Synopsys has extended its adaptive scan technology. Figure 1 illustrates the architecture. In addition to the CODEC logic, DFTMAX compression synthesizes high-speed, low-pin tester interfaces and the associated clock control logic (not shown).
Fig. 1: Adaptive scan technology architecture
Scan input data is deserialized at the ATE shift clock frequency and fed into the decompressor, and scan data exiting the compressor is re-serialized, again at the ATE shift clock frequency.
Deserialization of the data ensures that a sufficient number of inputs are available to the decompressor to minimize scan data dependencies and maintain high tolerance to unknown logic values propagating through the circuit.
Separate clocking of the internal scan chains in the CODEC limits power consumption during shift to appropriate functional levels when pin-limited compression is used in conjunction with power-aware test capabilities in the Synopsys test solution.
For added flexibility, DFTMAX compression supports both serial and parallel loading of scan data in a single implementation. Whether designers synthesize compression top-down or bottom-up, the implementation flows are unchanged.
Over-clocking to reduce test time In conjunction with the hardware IP, optimizations in TetraMAX ATPG enable high test time reduction with no loss in test coverage, even for test pin counts down to a single scan channel.
Still, further reductions in test time can be achieved by simply increasing the ATE shift clock frequency while leaving the internal scan shift frequency unchanged. Because the test pin interface circuits provide additional timing margin, they can operate at extremely high frequencies.
"Over-clocking the test pin interface in this manner reduces test time by the same proportion without impacting power consumption during shift. Figure 2 illustrates this principle by showing how increasing the frequency of the ATE shift clock by 2x and 4x affects test time.
Fig. 2: Test time versus compression ratio at increased ATE shift clock frequencies (1x, 2x and 4x)
One of Wolfson's latest designs, the WM8944 low-power hi-fi audio CODEC (figure 3) encapsulates powerful DSP functions.
These include 5-band equalization, dynamic range control and the Wolfson ReTune feature, a sophisticated digital filter that can compensate for imperfect characteristics of the housing, loudspeaker or microphone components in an application.
Fig. 3: Block diagram of the WM8944 audio CODEC.
The digital circuitry contains about F = 5600 scan flops and only enough digital pins to accommodate one scan input/output pair. Due to the increased gate count and extensive use of latches throughout the design, the ATPG pattern count is higher than the previous generation of ICs, approximately P = 2000 stuck-at patterns without compression.
Wolfson's mixed-signal tester allocates memory strictly on a per-pin basis, with a limit of 4Mb per pin. For each stimulus bit, storage is required for two scan response bits: one is the response bit itself and the other a mask or measure bit needed to determine if the response bit should be compared.
This means that the 4Mb allocated to the output pin needs to store at least twice the scan data volume. The minimum TDVR requirement is:
(Test data volume)/(ATE memory limit) = (2áFP)/(1 output piná4Mb/output pin)) = (2á5600á2000 b)/(4Mb) = 21.4Mb/4Mb = 5.3
To implement DFT for this design, Wolfson's engineers used DFTMAX compression enhanced for pin-limited testing, synthesizing a 5-bit interface between the CODEC and the single available scan channel.
As a result, 10x TDVR/TATR was achieved'more than enough to exceed the minimum TDVR requirement and reduce test time by another 42 percent. Because the analogue test time was dominant for this design, over-clocking the test pin interface to further reduce digital test time was not needed.
The DFT implementation task required just two days of engineering effort. As Wolfson migrates to smaller process geometries, DSM tests as well as stuck-at tests will be needed to maintain high defect coverage levels, driving TDVR requirements well above 5x for designs of similar digital complexity.
In a "what-if experiment to evaluate the potential for realizing higher compression, designers used DFTMAX compression to implement an 8-bit serial interface on the WM8944, achieving 18x TDVR/TATR with a single scan channel.
Although the adaptive scan architecture can support much higher compression levels, the result demonstrated that Synopsys' solution for pin-limited testing will meet Wolfson's requirements for the next generation of products.
Actual TDVR/TATR achieved depends on the compression ratio x, which is the number of internal scan chains divided by the number of test data I/O pairs.
Assuming the scan chains are well-balanced, test cycle count T is approximately: TÀ(F/C)á(P/x)
where F is the number of scan flops, C is the number of scan channels (I/O pairs) and P is the number of ATPG patterns in the test. Figure 4 illustrates the relationship between test time and compression ratio for a hypothetical design.
Fig. 4: Test time and compression ratio for a hypothetical design.
As shown by the upper (blue) curve, test time remains at a constant level, T0, up to the compression ratio xc required to load the complete pattern set into memory . Test time is constant up to this level because each unit increase in compression makes "room for more patterns in memory that must be tested, exactly offsetting any potential reduction in test time.
Increasing compression above this level reduces test time according to the above equation because the entire pattern set can now be loaded into memory. If there is less memory to store patterns, more compression is needed to load the complete test into memory, as indicated by the lower (red) curve.
The higher the TDVR ratio xc, the lower the incremental cost saving derived from increasing compression above this level.
Figure 5 reveals what happens to test time when the number of scan channels is reduced, assuming the amount of memory per channel remains the same. Because total ATE memory has been reduced, the TDVR ratio xc increases, as depicted by the upper (red) curve.
Fig. 5: Evolution of test time for a reduced number of scan channels.
And since there are fewer and longer internal scan channels, test time reduction diminishes at a lower rate.
About the authors
Chris Dodd is a principal design engineer in Wolfson Microelectronics' Corporate Engineering group - www.wolfsonmicro.com. He has 17 years' experience across a range of disciplines including digital design, design-for-test, test development and product engineering.
Chris Allsup is a marketing manager in Synopsys' synthesis and test marketing group * www.synopsys.com. He has more than 20 years' combined experience in IC design, field applications, sales and marketing.
 R. Kapur, S. Mitra, T. W. Williams, "Historical Perspective on Scan Compression, IEEE Design & Test of Computers, Volume 25, Issue 2, March-April 2008, pages 114-120.
 C. Allsup, "The Economics of Implementing Scan Compression to Reduce Test Data Volume and Test Application Time, Proc. International Test Conference, Lecture 2.2, 2006.
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