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Using compression to meet pin-limited test requirements

January 21, 2010 //

Timely delivery of highly reliable semiconductor products to market is essential to success in todays competitive business environment. As if following through on this objective were not already challenging enough, companies today are facing yet another challenge: fewer pins available for digital testing.


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Timely delivery of highly reliable semiconductor products to market is essential to success in today's competitive business environment.

As if following through on this objective were not already challenging enough, companies today are facing yet another challenge: fewer pins available for digital testing.

This article looks at the potential impact that availability of fewer test pins has on test quality and cost, and how one company, Wolfson Microelectronics, is using new technology in Synopsys' DFTMAX compression to simplify the task of pin-limited testing.

Growing pressure for scan compression
Over the past decade, advances in design automation technology have led to the widespread adoption of on-chip test data compression as an efficient means to improve test quality and lower the costs of testing digital integrated circuits (ICs).

Scan compression [1] reduces test data volume compared with conventional scan testing, freeing up automatic test equipment (ATE) memory for additional test patterns that improve defect screening.

It is no coincidence that the "mainstreaming of compression technology has coincided with the widespread use of pattern-rich deep-submicron (DSM) tests that identify subtle defects in nanometer-scale manufacturing processes.

Moreover, scan compression significantly reduces the time needed to test a device, which can dramatically lower the cost of high-volume production testing.

Compression requirements, however, continue to evolve across the semiconductor industry. Increased focus on packaging costs and tighter form factors for portable applications are leading to more stringent packaging constraints that limit the number of pins available for scan compression.

In many cases there are a sufficient number of pins available at wafer probe, but few pins remain accessible for subsequent testing of packaged parts.In an effort to further reduce costs at the tester, designers are increasingly employing compression with multi-site testing, a technique that tests multiple die simultaneously.

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