Verdi debug software now supports extensive Universal Verification Methodology
May 02, 2011 // Julien Happich
SpringSoft announced comprehensive support for the Universal Verification Methodology (UVM) with its Verdi Automated Debug System. The Verdi software adds UVM source code and new transaction recording capabilities to its existing HDL debug platform, making it easier for engineers to visualize and debug the complex SystemVerilog testbench structures required to test sophisticated system-on-chip (SoC) devices.
UVM is becoming an industry standard approach to ensuring the reusability and interoperability of testbench code (also referred to as verification IP), integrated from multiple sources or developed using different methodologies. The Verdi UVM capabilities are enabled within the system's unified testbench and design debug environment for more efficient recording and viewing of transaction data, beyond what is supported by the current UVM infrastructure.
With the ability to visualize a broader range of information between the testbench and design under test at the transaction level, Verdi users have a more complete picture of their environment, which is especially critical during detailed regression testing phases. SpringSoft implemented full UVM source code support with the industry standard SystemVerilog library. In addition, the company provides a custom SystemVerilog file in the Verdi system to transparently record all UVM transactions into the company’s defacto standard Fast Signal Database (FSDB) for a complete record of the traffic between testbench components.
The transaction data can be used within the existing Verdi waveform tool or in a new Unified Modeling Language (UML)-based sequence diagram view. The automated mechanism eliminates the need for manual recording processes, such as the output of transactions as text messages and instrumentation of testbenches to print transactions into a text file.
Key features of the new UVM testbench debug capabilities include a tabular spreadsheet view for highlighting and filtering the transactions, easy-to-use class browsers for navigating testbench hierarchy, and automated tracing through source code to identify the origin of testbench problems. As UVM use models continue to evolve and gain broad industry adoption, SpringSoft will extend its Verdi support with dynamic data dumping capabilities as well as more advanced automation to record different kinds of data and create additional views.
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Internet of Things (IoT) manufacturer Ciseco has launched the Raspberry Pi ‘Wireless Inventors Kit’ (RasWIK), featuring 88 pieces to provide everything a Pi owner needs to follow a series of step-by-step projects or to create their own wireless devices, without the need for configuration or even writing code.
RasWIK has been designed to be highly accessible, demystifying the dark art of wireless and enabling anyone with basic computing skills to begin building wireless devices with a Raspberry Pi. You can create anything from a simple traffic light, to a battery monitor, or even a temperature gauge that sends data to the Xively IoT cloud so billions can access the data.This month, Ciseco is giving away twelve Raspberry Pi Wireless Inventors kits, worth £49.99 each for EETimes Europe's readers to win.
And the winners are...
In our previous reader offer, Farsens was giving away five kits for EEtimes Europe readers to evaluate its FenixVortex, Kineo and X1 wireless, battery free sensor tags.
Lucky winners include Mr A. Neil from the UK, Mr. E. Delvaux from Belgium, Mr Lengal from the Czech Republic, Mr H. Bijlsma from the Netherlands, and Mr G. Pfaff from Germany. All should be receiving their packages soon. Lets wish them some interesting findings with their projects.
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