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Virtualization pushes into microcontrollers

February 24, 2014 // Nick Flaherty

Virtualization pushes into microcontrollers

Virtualization is set to be the next battlefield for microcontroller technology.


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Both MIPS and ARM are bringing virtualization to industrial microcontrollers in different ways. Imagination Technologies is rolling out the worlds first MCU cores that incorporate hardware virtualization, while ARM is preparing its own version of virtualization technology for the embedded market.
The MIPS M-class M51xx cores form the first group of entry-level MIPS Series5 Warrior CPUs for industrial control, Internet of Things (IoT), wearables, cloud computing, wireless communications, automotive, storage and other applications.
With the MIPS Series5 M-class IP cores, we believe were bringing fresh thinking to the embedded world, said Tony King-Smith, EVP marketing at Imagination. We have seen the trends leading to the need for more advanced multi-context security and multiple execution domains right across the CPU spectrum, which is why were now rolling out virtualization across our entire range of MIPS Series5 CPUs, including the new entry-level M51xx family.
The performance and low power credentials of our latest M-class CPUs have already generated a lot of excitement with our key licensees and partners, he said. With advanced functionality such as virtualization, full FPUs and advanced DSP capabilities, complemented by mature tools both from ourselves and our ecosystem partners such as Mentor Graphics and Green Hills Software, were confident youll be hearing a lot more about MIPS embedded CPUs in the coolest and most disruptive chips and products.
Virtualization is also at the heart of the next version of the Cortex-R which was announced last October and is very much aimed at industrial customers who want the performance of microprocessor in a microcontroller, says Richard York, vice president of embedded CPU marketing at ARM.
We are still not ready yet to say what form the implementation will take but the construction of that has happened, he said. It needs to be thoroughly built before we talk to the world about it. We took that to companies such as Green Hills and they in particular have been great and crawling all over it with their virtualization hat on and they see it as spot on. Its people like Green Hills that will make it a success or not if they cant make their virtualization work its a non-starter.
The first available M-class cores are the M5100 and the M5150. The M5100 integrates a real-time execution unit and SRAM controller, and is optimized for low-cost, low-power microcontroller applications. The M5150 incorporates the same execution unit as the M5100, and adds a programmable L1 instruction and data cache controller, as well as memory management support for high-performance Linux and RTOS embedded system applications.
The M-class cores implement the MIPS Release 5 architecture incorporating hardware virtualization. The M51xx cores are based on the same 5-stage pipeline architecture and leverage the high performance, comprehensive digital signal processing (DSP)/SIMD features of the previous generation MIPS microAptiv family of cores, along with the microMIPS Instruction Set Architecture (ISA) which provides up to 30% code size reduction over 32-bit only code.
The addition of hardware virtualization to MCU-class cores provides increased security and reliability for a wide range of applications allowing multiple, unmodified, operating systems and applications can run independently and securely at the same time on a single, trusted platform. This delivers a range of benefits for system development, including the ability to execute multiple tasks in isolation, intelligent resource allocation across several guests, secure downloads and uploads and IP protection.
Built-in prioritization mechanisms in the MIPS virtualization architecture, with support for up to seven secure/non-secure guests, enable it to optimally support real-time functionality. In space-constrained, low-power systems such as IoT or wearable devices, virtualization could be used to implement a multiple-guest environment where one guest running a real-time kernel manages the secure transmission of sensor data, while another guest, under RTOS control, can provide the multimedia capabilities of the system. For applications that demand an even higher level of security, the new M-class cores include tamper resistant features that provide countermeasures to unwanted access to the processor operating state. A secure debug feature increases the benefit by preventing external debug probes from accessing and interrogating the core internals.
The new M51xx cores also feature a Floating Point Unit (FPU) option supporting both single and double precision instructions for improved control systems processing. The FPU is well-proven, having been implemented in high-end MIPS cores.
Several hypervisors for the M-class cores are under development from Imagination and leading third party hypervisor developers, enabling customers to take full advantage of the hardware virtualization features. This includes several open source hypervisors such as KVM, the Kernel-based Virtual Machine, and a microkernel hypervisor, both of which are available now for the M5150 core.
The MIPS M5150 and M5100 cores are available for licensing now. Details of ARMs Cortex-R implementation are due later in the year.
www.imgtec.com
www.arm.com

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