Print  |  Send  |   

Xilinx breaks the 2 Tbps bandwidth barrier with transceiver-packed Virtex-7 X690T FPGAs

March 30, 2012 // Julien Happich

Xilinx breaks the 2 Tbps bandwidth barrier with transceiver-packed Virtex-7 X690T FPGAs

Xilinx announced the first shipments of its Virtex-7 X690T FPGA, combining what the company claims to be the industry's most reliable high-speed serial transceivers, highest system bandwidth, and market-optimized FPGA resources.

The Virtex-7 X690T FPGA is the first of a set of devices in the 7 series to address advanced high-performance wired communication applications that require low power, single-chip solutions. These devices enable fast, scalable and easy-to-implement chip-to-chip serial interfaces, robust 10GBASE-KR backplanes that maximize bandwidth while supporting the various board-to-board distances of next-generation communication systems, and high signal-integrity interfaces to the latest optical modules validated to support cable distances of up to 80km. Customers who need even greater system capacity and bandwidth can easily migrate to the Virtex-7 X1140T FPGA, built using 3D Stacked Silicon Interconnect technology on the 7 series FPGA scalable optimized architecture. Shipments of footprint-compatible Virtex-7 X1140T FPGAs with 96 GTH transceivers will follow in May.

The FPGAs can be used to implement advanced packet processing, FEC, quality-of-service, switching, and traffic management algorithms as well as next generation EdgeQAM. Engineers can the dynamically controllable GTH serial transceivers, including fully programmable three-tap FIRs that enable the transmitter de-emphasis needed to deal with the widest range of environments, along with fully-adapting seven fixed and four sliding tap receiver decision feedback equalization (DFE) circuits. To accelerate design and debugging, each GTH transceiver also includes a non-destructive, high-resolution 2D eye scan circuit that allows designers to see and measure the receiver eye from within the FPGA. With 80 GTH transceivers that run up to 13.1 Gbps, the Virtex-7 X690T FPGA is first FPGA to break the 2 Tbps single FPGA device bandwidth barrier. By leveraging the advanced 7 series FPGA architecture built on the TSMC 28HPL process, customers can save greater than 25 percent total power over competing similar-density FPGAs, allowing them to achieve the integration they need to build next-generation systems that achieve performance and low power requirements. Virtex-7 X690T FPGA engineering samples are available today.

Visit Xilinx at


All news


Follow us

Fast, Accurate & Relevant for Design Engineers only!

Technical papers     

Linear video channel


Read more

This month Ambiq Micro is giving away five of its 'Apollo EVB' evaluation boards, worth 9 each for EETimes Europe’s readers to assess the capabilities of their cutting-edge Apollo sub-threshold microcontroller.

The new suite of Apollo MCUs is based on the 32-bit ARM Cortex-M4 floating point microcontroller and redefines 'low power' with energy consumption that is typically five to...


Design centers     

Infotainment Making HDTV in the car reliable and secure

December 15, 2011 | Texas instruments | 222901974

Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.


You must be logged in to view this page

Login here :