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Xilinx lays grounds for 16nm FPGAs with new architecture

Xilinx lays grounds for 16nm FPGAs with new architecture

Technology News |
By eeNews Europe



The company announced its UltraScale Multi-Processing Architecture for what it says will be the industry’s first All Programmable MPSoCs.


“Moving from 28 and 20nm to 16nm, we had to deploy a new architecture that would truly support heterogeneous multi-processing” explained Steve Glaser, Senior VP of Corporate Strategy & Marketing at Xilinx who hinted at more dedicated acceleration engines, partly in software and partly in distributed hardware blocks.


In principle and to be future-proof, the new architecture could also make room for truly heterogeneous die stacks for cost-efficiency too.


The company looks at compute-intensive yet energy-efficient designs, in wireless and wired communications, in data centers, in M2M, in smart-vision.

These fields call for data pre-processing, evolving video-processing algorithms, analytics. With its UltraScale MPSoC architecture, the company will provide processor scalability from 32- to 64-bits with support for virtualization. Scalability includes CPU, interconnect, peripherals, processing engines and address space to Terabytes, according to Xilinx’ preliminary specs.

 

Glaser would not reveal how the fabric will be organized, but said that various flavours of the 16nm Zynq UltraScale MPSoCs would be available to account for the different processing requirements of these vertical markets, with different grouping options of the hardware accelerators to deliver “the right engine for the right tasks” as their promotional brochure says.


The new architecture will also include Xilinx’ next generation coherent interconnect and memory sub-system, for maximum system level performance, memory bandwidth and acceleration.


The company also promises advanced power management, and various technology enhancements to deliver multi-level security, safety and reliability.

Moving to TSMC’s 16nm FinFET process, Xilinx expects designers to gain a 60% improvement in performance/Watt over 28nm process technology. A better use of specialized engines partly accelerated in hardware (say for waveform processing, video or graphics processing, encryption, real time control) could cut die cost by up to 40% according to the FPGA vendor, while increasing performance from 5 to 10 folds compared to generalized architectures.  

No particular date was visible on the company’s roadmap, always cautious to announce its chips only when those are fully commercially available. But the company plans to launch its first UltraScale MPSoC devices for "Smarter Control", then "Smarter Vision" to follow-up with products dedicated to "Smarter Networks".


These new architectural elements are coupled with the Vivado Design Suite and abstract design environments. This includes C, C++, and OpenCL based design abstractions, third party system level abstractions from Mathworks and National Instruments, and IP based design abstractions and automation.

 

Visit Xilinx at www.xilinx.com

 

 

Related articles:

Xilinx confirms product plans at 20nm: previews 4.4M logic cell FPGA

Xilinx unveils new device families sharing a unified 28nm architecture roadmap

Xilinx ships the first parts in its Zynq-7000 extensible processing platform

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