Xilinx unveils new device families sharing a unified 28nm architecture roadmap
June 21, 2010 // Julien Happich
Following its recent move to TSMC's high-performance, low-power (HPL) process technology at 28nm, Xilinx is aggressively broadening the reach of programmable logic into the traditional ASSP and ASIC markets with three new FPGA families on its roadmap, the low-cost low-power Artix-7, the Kintex-7, and the high-end Virtex-7 due to be sampling in Q1 of CY2011.
The company started developing these devices two years ago, largely inspired from the Virtex 6 architecture, and all devices will be sharing a unified architecture to facilitate design migration and ease scalability within and between families.
By moving from the 40nm to the 28nm node and with power optimisation tools, Xilinx has focused on lowering static power as well as dynamic power in order to slash total power consumption by 50% compared with the previous generation. The 7 series will be the foundation for the next generation of Xilinx Targeted Design Platforms, which accelerate FPGA system development by aligning the key elements for FPGA design including ISE Design Suite tools, IP, boards, and targeted reference designs.
Xilinx's 28nm platform is based on the fourth-generation implementation of its Application Specific Modular Block (ASMBL) architecture with unique columnar technology, first introduced in the Virtex-4 FPGA family. All devices are designed with the same architectural building blocks (logic fabric, Block RAM, clocking technology, DSP slices, SelectIO technology) combined in differing proportions and optimized from the lowest to the highest device density and capability.
Twelve devices with densities ranging from 20K to 355K logic cells are in the pipeline for the lowest-power and lowest-cost Artix-7 family due to supplant Spartan 6 devices, while the best price/performance compromise will be achieved with a choice of five devices in the Kintex-7 family with logic densities ranging from 30K to 400K cells. The highest system performance and capacity with up to 2 million logic cells will be served by five different Virtex-7 devices.
In comparison to previous FPGA generations, Artix-7 FPGAs will offer 50% lower power and 35% lower cost with a 50% smaller footprint than Spartan-6 FPGAs, while Kintex-7 FPGAs will deliver Virtex-6 FPGA performance at less than half the price and 50% lower power. Virtex-7 FPGAs, meanwhile, will double system performance at 50% less power with a density of up to 2 million logic cells, which is more than any previous or existing FPGA, says the company.
Because the underlying architecture of all 28nm families is based on the widely adopted Virtex series architecture, the task of porting designs from the previous generation of devices, Virtex-6 and Spartan-6 FPGAs, is made significantly easier than in earlier generations.
Xilinx's EasyPath cost reduction program also guarantees Virtex-7 FPGA users an additional 35% cost reduction with no incremental conversion or engineering investment. With multiple unified FPGA families ranging from low cost to ultrahigh-end, developers can easily scale applications for system performance, capacity, or cost within and across the 28nm lines, all the while staying within power budgets.
The new FPGA families could enable developers to implement programmable solutions in a range of systems that had previously only been achievable in ASSPs or ASICs, including portable ultrasound equipment consuming less than 2 watts and automobile infotainment systems driven by 12 volts, as well as low-cost LTE baseband and femtocell base stations.
System manufacturers can leverage their investments in proprietary IP to rapidly expand product portfolios with higher-performance or lower-cost offerings to address the requirements of adjacent markets. Xilinx and its third-party IP providers can also more rapidly deploy broad-based IP across the entire breadth of the 28nm product line for a larger, more responsive FPGA development ecosystem.
This is critical going forward as Xilinx and its ecosystem partners build the 28nm generation of Targeted Design Platforms that assemble IP, reference designs, development tools, and boards into complete kits to help Xilinx customers reduce the costs and development time of implementing programmable solutions for an expanded range of low-cost to ultrahigh-end system applications.
Strict on the power budget
Xilinx looked at power from every angle, process, architecture, and software, to deliver 50% lower total power consumption and 65% lower static power for its 7-series FPGA families, compared with previous generations. It started with the silicon process.
Collaborating with TSMC, Xilinx helped to define a new 28nm high-k metal-gate (HKMG) process variant optimized for FPGAs and other core-logic devices that consumes less than half the static power of standard 28nm high-performance processes, while still meeting performance requirements for the most demanding applications. Xilinx engineers then implemented innovative architectural enhancements to lower dynamic power consumption by as much as 30% for core logic and I/O.
These enhancements range from the selection of transistor choices to achieve the target power reduction in every hard block, to the addition of low-power I/O modes that enable high system-bandwidth levels with significantly lower power consumption, including customer-selectable I/O modes that save additional power while I/O is idle.
For extra power savings, the latest ISE Design Suite software supports the 28nm FPGA families with intelligent clock-gating technology and fifth-generation partial-reconfiguration techniques that further lower dynamic power by as much as 30%. In addition, lower-power-grade device options with 0.9-volt Vcc provide additional 27% static power and 20% dynamic power reductions.
Xilinx's approach to reducing power consumption at 28nm also focused on eliminating wasted power to provide more usable performance, particularly for ultrahigh-end devices with up to 2.37 TMACs in DSP performance, 2 million logic cells at clock speeds up to 600 MHz, and as much as 2.4 Tbits/second of high-speed connectivity.
The company has improved all of the FPGA components that contribute to system performance and balanced them to achieve record-breaking levels, including 2.5X more logic, which helps to run more operations in parallel, and 1.9X more DSP for internal core signal or data processing. For internal data buffering, the 7 series has 1.7X more internal BRAM, which can be turned off when not in use to save power. For external memory interfacing, there is DDR3 capability at 2,166 Mbps, which is double the performance of Virtex-6 FPGAs and the highest in the FPGA industry.
In fact, overall I/O throughput is the highest ever compared with previous generations, with 1.2X more parallel bandwidth and 1.6X more serial bandwidth, providing over 1.9 Tbps of I/O. Xilinx also increased both the performance and the number of embedded serial transceivers, with line rates up to 13.1Gbps supporting up to 80 transceivers in a single FPGA.
More information on Xilinx's unified 28nm architecture and the 7-series FPGA families at www.xilinx.com/7
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