Xilinx unveils new device families sharing a unified 28nm architecture roadmap
June 21, 2010 // Julien Happich
Following its recent move to TSMC's high-performance, low-power (HPL) process technology at 28nm, Xilinx is aggressively broadening the reach of programmable logic into the traditional ASSP and ASIC markets with three new FPGA families on its roadmap, the low-cost low-power Artix-7, the Kintex-7, and the high-end Virtex-7 due to be sampling in Q1 of CY2011.
The company started developing these devices two years ago, largely inspired from the Virtex 6 architecture, and all devices will be sharing a unified architecture to facilitate design migration and ease scalability within and between families.
By moving from the 40nm to the 28nm node and with power optimisation tools, Xilinx has focused on lowering static power as well as dynamic power in order to slash total power consumption by 50% compared with the previous generation. The 7 series will be the foundation for the next generation of Xilinx Targeted Design Platforms, which accelerate FPGA system development by aligning the key elements for FPGA design including ISE Design Suite tools, IP, boards, and targeted reference designs.
Xilinx's 28nm platform is based on the fourth-generation implementation of its Application Specific Modular Block (ASMBL) architecture with unique columnar technology, first introduced in the Virtex-4 FPGA family. All devices are designed with the same architectural building blocks (logic fabric, Block RAM, clocking technology, DSP slices, SelectIO technology) combined in differing proportions and optimized from the lowest to the highest device density and capability.
Twelve devices with densities ranging from 20K to 355K logic cells are in the pipeline for the lowest-power and lowest-cost Artix-7 family due to supplant Spartan 6 devices, while the best price/performance compromise will be achieved with a choice of five devices in the Kintex-7 family with logic densities ranging from 30K to 400K cells. The highest system performance and capacity with up to 2 million logic cells will be served by five different Virtex-7 devices.All news
Microchip in Pursuit of CSR
September 01, 2014
It’s official. Microchip Technology CEO Steve Sanghi, once known as a skeptic on the Internet of Things, wants to join the ...
Samsung Funds III-V FinFETs in US Lab
A question of Europe
Trinamic's stepper motor package gets you started
Winged parcel delivery: Google's way
Two-inch Super AMOLED display fits Samsung smartwatch plans
August 29, 2014
Samsung is gearing up for a face-to-face confrontation with Korean rival LG with the introduction of the Samsung Gear S smartwatch ...
UK armed forces consider lithium sulfur batteries
Small cell market to hit $4.8 billion in five years
Dutch startup shrinks 60GHz radars, increases precision
- Power Modules: The New Super Power
- Digital Power Management Reduces Energy Costs While Improving System Performance
- Using RF Recording Techniques to Resolve Interference Problems
- How to Protect & Monetize Android Apps
InterviewA question of Europe
Sir Peter Bonfield sits on the board and has advisory roles in many international companies and universities. With more than 45 years of experience in electronics, computers and communications, here he ...
Filter WizardCheck out the Filter Wizard Series of articles by Filter Guru Kendall Castor-Perry which provide invaluable practical Analog Design guidelines.
Linear video channel
READER OFFERRead more
This month, Trinamic Motion Control is offering you to win one of four TMCM-1043 development kits for its highly integrated, NEMA 17-compatible TMCM-1043 stepDancer stepper motor module.
Offering designers an easy-to-use PC-based GUI that allows one-click modification of motor drive current, micro-stepping and other key parameters, the intuitive kits are custom designed and developed for...Read more
December 15, 2011 | Texas instruments | 222901974
Unique Ser/Des technology supports encrypted video and audio content with full duplex bi-directional control channel over a single wire interface.