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Xilinx unveils new device families sharing a unified 28nm architecture roadmap

June 21, 2010 // Julien Happich

Xilinx unveils new device families sharing a unified 28nm architecture roadmap

Following its recent move to TSMC's high-performance, low-power (HPL) process technology at 28nm, Xilinx is aggressively broadening the reach of programmable logic into the traditional ASSP and ASIC markets with three new FPGA families on its roadmap, the low-cost low-power Artix-7, the Kintex-7, and the high-end Virtex-7 due to be sampling in Q1 of CY2011.

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The company started developing these devices two years ago, largely inspired from the Virtex 6 architecture, and all devices will be sharing a unified architecture to facilitate design migration and ease scalability within and between families.

By moving from the 40nm to the 28nm node and with power optimisation tools, Xilinx has focused on lowering static power as well as dynamic power in order to slash total power consumption by 50% compared with the previous generation. The 7 series will be the foundation for the next generation of Xilinx Targeted Design Platforms, which accelerate FPGA system development by aligning the key elements for FPGA design including ISE Design Suite tools, IP, boards, and targeted reference designs.

Xilinx's 28nm platform is based on the fourth-generation implementation of its Application Specific Modular Block (ASMBL) architecture with unique columnar technology, first introduced in the Virtex-4 FPGA family. All devices are designed with the same architectural building blocks (logic fabric, Block RAM, clocking technology, DSP slices, SelectIO technology) combined in differing proportions and optimized from the lowest to the highest device density and capability.

Twelve devices with densities ranging from 20K to 355K logic cells are in the pipeline for the lowest-power and lowest-cost Artix-7 family due to supplant Spartan 6 devices, while the best price/performance compromise will be achieved with a choice of five devices in the Kintex-7 family with logic densities ranging from 30K to 400K cells. The highest system performance and capacity with up to 2 million logic cells will be served by five different Virtex-7 devices.

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