3D TSV chip market to grow more than 10 times faster than the global semiconductor industry, says Yole Développement

July 26, 2012 // By Julien Happich
In its 3DIC & TSV Interconnects 2012 Business Update report, Yole Développement provides an update of the 3DIC & TSV technology market and define the market forecast for the next 5 years, providing a deeper understanding of the supply chain challenges and moves that are currently happening in this “middle-end” industry space.

“Last year, the market value of all the devices using TSV packaged in 3D in the 3DIC or 3D-WLCSP platforms (CMOS image sensors, Ambient light sensors, Power Amplifiers, RF and inertial MEMS) was worth $2.7B. It will represent 9% of the total semiconductor value by 2017, hitting almost $40B,” explains Lionel Cadix, Market & Technology Analyst, Advanced Packaging at Yole Développement. 3DIC which typically uses TSV 'via middle' for memory and logic IC stacking is expected to grow the fastest in wafers as well as in overall value, whereas 3D WLCSP will continue growing at a 18% CAGR.

3D WLCSP is the preferred solution today for the efficient assembly of small-size optoelectronic chip like CMOS image sensors. It is also the most mature 3D TSV platform at the moment as Yole Développement estimates the market to be about $270M in 2011 for the “middle-end” processing factories serving this specific market. More than 90% of the revenues in this area come from low-end and low resolution CMOS image sensors manufacturing (typically CIF, VGA, 1MPx and 2MPx sensors). Xintec in Taiwan is the leader for 3D WLCSP packaging today, followed by China WLCSP, Toshiba and JCAP.

Most of the players provide 3D WLCSP services based on a 200mm wafer-level-packaging industrial infrastructure. Important investments are still expected from major companies to move to 300mm. Indeed, this trend will be necessary to move to the high-end CMOS image sensors market (> 8MPx resolution) where sensors are today on the transition from backside illumination to real 3DIC packaging architecture. This latest architecture will be soon called " 3D BSI ", where photodiodes will be vertically stacked directly onto the DSP / ROIC wafer and connected by the mean of TSVs.

3DIC technology is foreseen today as a new paradigm for the future of the semiconductor industry as it will enable several more decades of chip evolution at ever lower cost, higher performance and smaller size