AMS updates 180nm CMOS physical design kit

July 22, 2016 // By Peter Clarke
AMS AG (Premstaetten, Austria) has released version 4.14 of its 180nm CMOS physical design kit with improved transistors.

The 180nm CMOS speciality process, known as aC18, has been transferred into being AMS's 200mm wafer fab facility in Austria.

The updated PDK provides improved analog features and device performance. It supports 1.8 and 5.0V NMOS and PMOS devices (substrate based, floating, low leakage and high threshold voltage options) and fully characterized passives including various capacitors.

The PDK supports gate densities of up to 152kgates per square millimeter, updated digital and analog I/O libraries with up to six metal layers as well as ESD protection cells with up to 8kV HBM level. One-time programmable memories (OTP), online memory generation service for RAMs and ROMs as well as a zero-mask-level-adder EEPROM IP block (up to 8kbit) complete the offering.

"It’s a milestone for us to bring our aC18 technology online in our Austrian fab," said Markus Wuchse, general manager of the AMS foundry division.

The aC18 specialty process is suitable for sensors and sensor interface devices in a wide variety of applications such as wearables, healthcare, home automation, smart cars and industry 4.0, AMS said.

www.ams.com