In analog, EDA tools cannot replace common sense

May 26, 2016 // By Brandt Braswell
Brandt Braswell
Brandt Braswell, a distinguished member of the technical staff at NXP Semiconductor, discusses automated "optimizers" for analog design and their shortcomings.

I know there have been many advances in software development for use in design projects. The digital design landscape has permanently been altered by the use of sophisticated software tools for use in design. Design tasks that used to take months can now be completed in days. Although these tools can still provide erroneous results if the setups are incorrect or the models and assumptions are flawed, the errors have vastly been reduced to the point of becoming an exception and not the norm.

The use of place and route software tools have also made completing large digital layouts as easy as running scripts for place and route with interactions for static timing analysis for meeting critical setup and hold requirements for digital blocks.

Is this the same for analog design? Are there equivalent tools for designing and completing layouts for analog blocks? Over the years I have seen tools, optimizers, called in to do the work of skilled analog design engineers. Many of the tools have made significant progress in helping designers make faster and timelier decisions. However, I do not believe that the time of replacing the analog engineer is here and won't be for some time.

The current state of the tools means the tools cannot replace an engineer’s raw intuition for designing complex analog blocks. However, I do believe that optimizers do have their place for low-level simple analog design blocks that have loose or less stringent specifications.

When it comes to complex analog design, "you need to be able to walk with the electrons," as a senior colleague said to me one time, to solve design problems and layout constraints.

Often times the appropriate solution requires different topologies or innovation. This cannot be handled by an optimizer that will optimize based on a given set of parameters and a given circuit topology. The optimal solution to the problem may need an innovative combination of known