Analog synthesis remains remote

July 15, 2014 // By Keith Sabine
Keith Sabine, product manager at EDA firm Pulsic, discusses the advantage of considering layout and placement at the same time in analog EDA.

Today designers are facing increasing pressure to reduce design time and time-to-market. In the digital world, automation has long been used to enable turnaround of ever-larger designs in a reasonable timescale. Designers can estimate parasitics early in the design flow – at the RTL level – to see if they meet timing and power criteria. Thus design changes can be iterated relatively quickly until the design goals are met, with detailed layout following.

 

In the analog world, early estimation of parasitics has not been traditionally possible. Circuit simulation without parasitics extracted from real layout gets less and less useful in predicting performance as geometries have shrunk. Layout-dependent effects are difficult to estimate, and so the designer may have to wait days for the layout, and hence the parasitics, when layout is done manually. It requires an experienced analog layout engineer to take into account the matching of devices and the topologies required to give good performance, and they usually have only time to explore one layout topology. So the circuit design and layout are iterative. This is obviously not an ideal situation.

 

EDA companies have recently renewed efforts to bring automation to analog layout. So, for example, Helix from Ciranova (now Synopsys) and Modgens (from Cadence) are efforts to create more automation in the analog layout flow. The traditional digital philosophy of placing components, then routing them, has been found to be lacking, and existing tools are often called "analog prototyping" solutions. The problem lies in the fact that running placement without knowing the routing is difficult – the resulting placement may not be routable, or may not be dense enough.

 

New analog automation technology addresses this problem by considering the placement and routing as a single problem, a process known as PolyMorphic Layout. In fact, not just one solution is generated, but multiple layout topologies, each of which can be extracted and simulated to determine the