The IP set does not include support for extreme ultraviolet (EUV) lithography, which is expected to be deployed later.
"The physical IP platform is available for tape outs in 1H17. We see some engineering samples in 2017," Ron Moore, vice president of marketing in the physical design group at ARM, told EE Times Europe. However, it is not clear that there is a performance, power or area benefit in selecting the 7FF process over the 10FF process.
The 10FF was a marked scaling over 16FF+ that could produce a 20 percent speed increase at the same power, or more than 40 percent power reduction at the same speed, according to past reports (see TSMC Symposium: 10nm is ready for design starts). But it came at the cost of the increased use of double patterning.
Moore explained: "Basically TSMC has two nodes that are distinctly different 16/14 and 10/7. For TSMC 7nm is the next generation from 10nm. But there are additional challenges such as lay-out rules and the electrical properties of transistors." You can expand that list to include process variation, routability, analysis for sign-off, timing variation and electromigration. And at 7nm without EUV there will be a requirement for triple patterning.
"We will have to redefine our cells to take account of EUV but 7FF is based on immersion lithography," said Moore.