Berkeley scientists shrink transistor gate to 1nm

October 07, 2016 // By Julien Happich
Publishing their findings in the journal Science, a research team led by faculty scientist Ali Javey at the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) have devised the smallest transistor ever reported.

The feat was realized by embedded a single carbon nanotube, 1nm in diameter in a thin layer of zirconium dioxide (ZrO 2) under atomically thin sheets of molybdenum disulphide (MoS 2), about 0.65 nanometers thick.


Schematic of a transistor with a molybdenum disulfide channel and 1-nanometer carbon nanotube gate. (Credit: Sujay Desai/UC Berkeley)

Only a proof of concept, the prototyped nanotransistor exhibited a switching behaviour and proves the 5nm barrier can be broken for gates. The researchers have yet to develop self-aligned fabrication schemes to reduce parasitic resistances in the device and open the way to scalable on-chip circuit engineering.


Transmission electron microscope image of a cross
section of the transistor. It shows the 1-nanometer
carbon nanotube gate and the molybdenum disulfide
semiconductor separated by zirconium dioxide,
an insulator. (Credit: Qingxiao Wang/UT Dallas)
 

Moving to MoS 2 as a transistor material for the channel instead of doped silicon, the researchers circumvented the tunnelling effects that would typically kick in when designing sub-5nm gate barriers. Electrons flowing through MoS2 are heavier, they explain, which allows smaller gates to control their flow. The work at Berkeley Lab was primarily funded by the Department of Energy’s Basic Energy Sciences program.

Visit Lawrence Berkeley National Laboratory at  www.lbl.gov

Access the paper at http://science.sciencemag.org/content/354/6308/99

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