The two companies have developed a new co-simulation interface between the latest version of Aldec's Riviera-PRO design simulation and verification platform used by FPGA, ASIC, and SoC development teams, and SystemVue, Agilent’s ESL design and signal processing environment used by system architects and algorithm developers in physical layer designs of wireless, RF and DSP applications. The new interface enables users to efficiently integrate algorithm and system-level designs with hardware implementations.
“Agilent system-level design products are now integrated into the hardware design flow, which enables system engineers to troubleshoot Verilog and VHDL hardware implementations, while still maintaining a higher-level view of physical layer (PHY) system performance,” said Daren McClearnon, Agilent’s SystemVue Product Marketing Manager. “Our respective R&D teams worked closely together to create a high-performance yet cost-efficient co-simulation interface that unites baseband, RF, simulations, and measurements in single, system-level cockpit.”
The new co-simulation interface requires only one instance of Riviera-PRO (regardless of the number of HDL blocks on a SystemVue diagram), supports a range of data types, and provides extensive cross-domain debugging capabilities. This tight, bi-directional integration reduces development time and effort by enabling continuous test and system-level verification throughout the development process.
“The Agilent SystemVue co-simulation interface brings several exciting new features to hardware design verification engineers, our traditional customers,” said Dmitry Melnik, Riviera-PRO Product Manager. “It enables the link to a powerful RF System simulator, RF EDA tools and models, trusted references for emerging communications standards, and even test and measurement equipment if necessary. Now engineers can re-use SystemVue components in hardware simulations while respective HDL blocks are being coded, or use SystemVue as a testbench to verify HDL implementation.”