In-chip supercaps could pack 50mF cm–2, says VTT

June 08, 2016 // By Julien Happich
Combining MEMS and nanofabrication techniques, researchers at the VTT Technical Research Centre of Finland have designed a CMOS-compatible micro-supercapacitor structure that leverages the typically unused silicon bulk of chips' substrates to store energy.

The supercap structure consists in microchannels etched in bulk silicon, whose sidewalls are treated to host a hybrid nanomaterial electrode consisting of Porous Silicon (PS) coated with a few nanometre thick titanium nitride layer (through an atomic layer deposition (ALD) process). The lateral thickness of the coated porous silicon layer as well as the length of the channels determine the capacitance of the whole structure expanding laterally within the chip substrate.

Conformal coating of PS is not straightforward due to very high aspect ratios which can reach 1:1000 and above, explain the researchers in a paper made available on Science Direct and to be published in Nano Energy this summer. But they tuned their ALD process to deposit a 10nm thick homogeneous layer of TiN inside the PS matrix. They then added contact pads and filled the trenches with a liquid electrolyte to obtain very efficient electrochemical double layer capacitors (EDLC) with almost ideal characteristics. This is thanks to the good electrochemical properties of TiN and the large area of the PS matrix, notes the paper.

What's more, the whole manufacturing process does not exceed 450°C, making it CMOS compatible, in effect turning the unused bulk silicon of planar chip designs into useful integrated energy storage pockets.

Characterizing a few prototypes, the researchers report a very high specific capacitance of 15Fcm−3, an energy density of 1.3mWh cm−3, and a power density up to 214W cm−3, all combined with a stability exceeding 13,000 cycles (Prunnila later added that so far the maximum number of recorded cycles had been 50,000 only limited by the measurement time, with no observable degradation for the porous Si-TiN electrode material.


In-chip PS–TiN supercapacitor. (a) SEM picture of the trenches separating the electrodes. (b) Schematic illustration of the cross-section of two opposite electrodes of a ready device (TiN coated PS layer and the aluminium contact pads on the back side are also present). (c) Higher magnification SEM picture of the porous regions. (d) Device trench side and (e) the metallization side containing aluminium contacts for supercapacitor electrodes. (f) Cyclic voltammetry curve at 100 mV/s (inset) and capacitance retention.