The new ASICs enable a more flexible set of interfaces for ports carrying 100Mbit to 100 Gbit/second Ethernet and 32 Gbit/s Fibre Channel traffic. The company claims the chips are the first to pack 36 100G ports in a system that fits in a single rack unit. The ASICs also implement flow control tables to monitor all traffic running across leaf and spine switches.
Cisco designed a family of three closely related ASICs for its systems with aggregate bandwidth ranging from 3.6 to 1.6 Terabits/second. Two of the chips, made in TSMC’s 16FF+ process, started shipping in systems in February, a third will ship within two months.
“We wanted the performance and cost advantages” of going to 16nm, Thomas Scheibe, senior director of product management for Cisco’s data center switch group told EE Times.
The process helps Cisco pack 20 to 40 MBytes of memory into the ASICs, eliminating the need for external memory. The cost of external memory “is significantly higher with lower reliability and higher power consumption” than embedded memory, said Scheibe.
Cisco, long one of the world’s largest ASIC designers, has its own approach for dynamically parsing the memory into shared or private buffers as needed. The memory serves the flow tables which are the largest new blocks in the ASICs. The tables help calculate average flow completion times, a key metric to avoid data collisions and get full use from its computer networks.
“Today no top-of-rack switch has a flow table for cost reasons and most chips can’t export the flow data fast enough,” said Scheibe.
The ASICs also let users select the data rates at which they want to run Ethernet and Fibre Channel traffic. They support SFP interfaces for 10G or 25G traffic and QSFP links for 40G or 100G links.
The switch team was the first to use 16nm process technology inside Cisco. Scheibe claims the ASICs were the first switch chips of any kind produced in a 16nm process.
The ASICs are relatively large, about the same size as Cisco’s prior 28nm switch chips. Die size is one of the gating items for switch chips, Scheibe said. He credits Cisco’s ASIC simulation tools for helping the company go from “first prototypes to shipping products in 6-8 months.”
Cisco is making two versions of its new switch systems. One uses Broadcom’s Tomahawk chips as a system fabric and line card switch; the other uses the new ASICs. Some customers demand merchant chips because they modify the software running on the systems to program their own networks, he said.
“Cisco believes a significant proportion of its datacenter-networking installed base will be receptive to the price-performance attributes and capabilities of the Nexus switches based on its new proprietary ASIC technology,” said Brad Casemore, an analyst following the sector for International Data Corp.
“They emphasized use cases that spotlight the flow tables, analytics, and flexible port configurations to position the technology for where the market is going…private and hybrid cloud, containers and microservices [and] distributed IP-based storage,” he said in an email exchange.