The advantage of having such high-performance converters in standard CMOS process technology is that it allows their integration on a single die together with a complex DSP and high-speed serial OTN framer interfaces to form a 100Gbps DP-QPSK transceiver. For such a device with 4 ADC and 4 DAC channels running at 65GSample/s, the sheer volume of data (2 Tbps) being converted to and from the analogue to the digital domain dictates a single die solution. Management of skew among the four signal component lanes is done in the digital domain allowing precision control that is very stable across processing, temperature or voltage variations in the transceiver device. Signal processing in the digital domain allows for compensation of non-linearities in the transmit optics chain, as well as mitigating signal reflections at the device IOs. Integration of the 4-channel DAC into a transceiver device also removes the requirement for a separate multiplexer/encoder device.
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