Compliance test suite addresses DDR4 and LPDDR3 logic analysis

September 11, 2012 // By Julien Happich
Agilent Technologies announced what the company claims to be the industry's only test suite for compliance testing of computer and embedded DDR/2/3/4 and LPDDR/2/3 memory applications.

With this software suite and an Agilent logic analyzer, digital designers can monitor DDR/2/3/4 or LPDDR/2/3 systems in real time to identify elusive, intermittent violations in protocol or bus-level timing. The new software allows users to customize tests, either by adding to existing test groups or by defining unique test groups of valid logic analyzer triggers for protocol or bus-level timing violations. Customized real-time compliance tests can be defined for any valid logic analyzer trigger, for any digital system probed by an Agilent logic analyzer.

The protocol debug and validation test suite includes three products: the Agilent B4621B, a bus decoder for DDR/2/3/4, the Agilent B4622B, a protocol compliance and analysis toolset for DDR/2/3/4 and LPDDR/2/3, and the Agilent B4623B, a bus decoder for LPDDR/2/3.

The B4621B bus decoder for DDR/2/3/4 debug and validation provides complete protocol decoding of memory transactions using an Agilent logic analyzer as the execution engine. The protocol-decoding software translates acquired signals into easily understood colorized bus transactions showing associated data bursts for double-edge data-rate captures up to 2.5 Gb/s.

The B4622B DDR/2/3/4 and LPDDR/2/3 protocol compliance and analysis toolset automatically captures real-time compliance protocol violations, detects post-process protocol violations on captured traces, takes performance measurements, and creates physical address triggers.

The B4623B bus decoder for LPDDR/2/3 debugging and validation is a complete protocol decoder of memory transactions for LPDDR/2/3 using an Agilent logic analyzer as the execution engine. The software translates acquired signals into easily understood bus transactions showing associated data bursts, for all LPDDR2/3 data rates. Valid read and write commands are decoded to include row and column addresses and the complete data burst associated with the command.

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