Analog circuitry is essential for all real-world systems. Sensors, for example, which are a primary driver for the growing IoT market, require analog for measurements, such as temperature, pressure, light levels, and so on, and for A/D and D/A converters to convert to and from the digital world. However, although digital design productivity has improved massively since the introduction of synthesis, advanced place and route and timing-driven design, analog design still relies on circuit simulation, manual layout and verification.
The bottleneck in the manual flow is that typically a circuit designer designs and simulates a block, then passes on the schematic to a layout engineer, who will take constraints from the circuit designer (often in notes in the schematic, e.g., “these devices need to be matched”) and perform a layout. It may take hours or even days to lay out the design, then hand back the parasitic information to the circuit designer to check the performance. If performance is not met, the loop continues – hence the bottleneck. Also, the designer might want an initial estimate of the block size in order to produce a floor-plan of the top level, which again requires a layout to be generated, maybe using a prototype layout in order to speed things up a little.
There have been several incremental improvements to the flow over the years – for example, the use of parameterized cells to automate device generation. However, automatic placement and routing of analog designs has been largely unsuccessful. Techniques such as placing based on the schematic require manual movement of devices, and, without routing knowledge, cannot give any accurate area estimation. Other placement techniques can achieve better results, but typically generate just one layout, which may or may not be routable, so again manual modification is required (which more often than not can be extensive).
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