Cost-optimized FPGA packs 500K logic elements, slashes power consumption

February 15, 2017 // By Julien Happich
Microsemi announced its cost-optimized PolarFire field programmable gate array (FPGA) product family, claiming to deliver the industry’s lowest power at mid-range densities with 12.7 Gbps Serializer/Deserializer (SerDes) transceivers.

In collaboration with Silicon Creations, Microsemi has developed a 12.7 Gbps transceiver fully optimized to be area efficient and low power, resulting in total power of less than 90 milliwatts at 10Gbps. With best-in-class low device static power of 25mW at 100K logic elements (LEs), zero inrush current and unique Flash*Freeze mode for a standby power of 130 mWs at 25ºC, PolarFire devices are up to 50 percent lower power than competing FPGAs for the same application, says the manufacturer. Microsemi also provides customers with a power estimator to analyze power consumption of their designs. After implementation, the SmartPower Analyzer can be used to access full design power. The devices offer inherent immunity to configuration SEUs. They come with built-in single error correction and double error detection (SECDED) as well as memory interleaving on large static random access memory (LSRAMs), and system controller suspend mode for safety critical designs.
PolarFire FPGAs offer Cryptography Research Incorporated (CRI) patented differential power analysis (DPA) bitstream protection, integrated physically unclonable function (PUF), 56 KB of secure embedded non-volatile memory (eNVM), built-in tamper detectors and countermeasures, true random number generators, integrated Athena TeraFire EXP5200B Crypto Co-processors (Suite B capable) and a CRI DPA countermeasures pass-through license. The devices come with up to 481K logic elements, up to 33 MBs of RAM and up to 1480 18x18 multiply accumulate blocks with hardened pre-adders.

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