The Palladium Z1 platform executes up to 2304 parallel jobs and scales up to 9.2 billion gates, addressing the growing market requirement for emulation technology that can be efficiently utilized across global design teams to verify increasingly complex systems-on-chip (SoCs).
The new platform comes with a unique virtual target relocation capability, and payload allocation into available resources at run time, avoiding re-compiles. A massively parallel processor-based architecture endows the Palladium Z1 platform with 4X better user granularity than its nearest competitor, the EDA company claims, while consuming less than one-third of the power that the Palladium XP II required per emulation cycle.
Full virtualization of the external interfaces through a virtual target relocation strategy enables remote access of fully accurate real world devices as well as virtualized peripherals like Virtual JTAG.
Pre-integrated Emulation Development Kits are available for USB and PCI-Express interfaces, providing modeling accuracy, high performance and remote access. Combined with virtualization of the databases using Virtual Verification Machine capabilities, it allows for efficient offline access of emulation runs by multiple users.
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