By providing both the DDR4 controller and the DDR4 PHY at that high speed, the company will allow designers to truly leverage DDR4 high-speed memories into servers, networking and consumer applications.
“In 28nm, there has been no DDR4 IP in the market that we are aware that has achieved any more than 2400Mbps”, commented Andrea Huse, Senior Marketing Manager at Cadence Design Systems. “In general, IP for DDR3 has been in the 2133 Mbps range on the high side and we are currently planning DDR4 – 3200 IP using a smaller geometry node” she added.
The DDR4 PHY IP will support higher densities than DDR3, but it has other significant advantages over DDR3, including greater reliability, better power efficiency operating from 1.2V instead of 1.5V for DDR3, higher capacity, explained the EDA vendor.
Reliability, availability, and serviceability (RAS) are more robust since DDR4 supports command and address parity error detection and recovery, command blocking upon detection of parity error, but also a connectivity test mode. DDR4 also provides optional features like CRC protection for write data.
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