EnSilica takes its IP to BaySand's ASIC UltraShuttle-65 MPW service

August 17, 2016 // By Julien Happich
Last month, BaySand was announcing a low-cost multi-project wafer (MPW) program, ASIC UltraShuttle-65, to support multiple designs customizable by 4 metal layers, yielding quality verified and fully tested ASICs.

The service was based on BaySand’s standard cell library, including logic cells, IOs, Memories and IP blocks, which are fully characterized and silicon proven, combined with BaySand’s RTL signoff design methodology that includes Design for Testability (DFT), Automatic Test Pattern Generation (ATPG), full scan, JTAG, BIST and physical implementation.

EnSilica has now teamed with BaySand so customers can also pick and choose from EnSilica’s eSi-RISC processor cores, eSi-Connect processor peripherals, eSi-Crypto encryption and eSi-Comms communications IP solutions as well hardware accelerators.

EnSilica says its automated flow allows complex CPU sub-systems to be delivered to customers in a matter of days. The sub-systems can include single or multiple eSi-RISC processor cores with JTAG debug, and a range of peripherals and timers as well as encryption accelerator cores to enable secure boot and communication.

The system is built around standard multi-layer AMBA AHB bus fabric generated as part of the automated flow. Additional APB, AHB, AXI buses can be included to allow the easy integration of the customer’s own IP cores.

This design flow allows EnSilica processor sub-systems to be delivered to customers well ahead of the first ASIC UltraShuttle-65 MPW run in October 2016, claim the new partners.

Visit EnSilica at www.ensilica.com

Visit BaySand at www.baysand.com