Floating point added to multicore DSP platform for MIMO support

February 19, 2013 // By Nick Flaherty
CEVA has added a suite of processor and multi-core technologies to its CEVA-XC DSP architecture framework for high performance wireless applications including wireless terminals, small cells, access points, metro and macro base-stations.

Among the new enhancements in CEVA MUST are support for multi-core features, high-throughput vector floating-point processing and a complete set of co-processor engines offering power-efficient hardware-software partitioning.
MUST is a cache-based multi-core system technology with advanced support for cache coherency, resource sharing and data management.
Initially available for the CEVA-XC, MUST supports the integration of multiple XC DSP cores in a symmetric multiprocessing or asymmetric multiprocessing system architecture, along with a broad range of technologies designed specifically for dynamic scheduling using shared pools of tasks, hardware event based scheduling defined via software and task and data driven shared resource management. It also adds memory hierarchy support with full cache coherency, automated data traffic management without software intervention, and a prioritization scheme based on task-awareness.
CEVA has also added extensive support to the CEVA-XC architecture framework for the ARM AXI4 interconnect protocol and AMBA 4 ACE cache coherency extensions to simplify the software development and debugging process for SoC designs and reduce the software cache management overhead, processor cycles and external memory bandwidth.
LTE-Advanced and 802.11ac use multiple input multiple output (MIMO) processing with multiple antennae transmitting and receiving data. To achieve ultra-high precision and optimal performance when processing these complex data streams, CEVA has added support for floating-point operations to the CEVA-XC vector processor unit, in addition to the traditional fixed-point capabilities. Floating-point operations are supported on full vector elements, processing up to 32 floating point operations in every core cycle along with a dedicated instruction set architecture (ISA) for high-dimension MIMO, including support for 802.11ac 4x4 use cases.
MUST includes a set of tightly-coupled extension (TCE) coprocessor units for Maximum Likelihood MIMO Detectors (MLD), 3G de-spreader units, FFT with NCO phase correction, DFT, Viterbi, HARQ combining, and LLR compression / de-compression. The tightly-coupled extensions use automated low-latency data traffic management between the DSP memory and the coprocessors to minimize DSP intervention and enable truly parallel co-processing.
“The suite of