Glass substrates to match semiconductor packaging requirements

January 19, 2017 // By Julien Happich
Glass and chemicals provider AGC Asahi Glass has developed a new line of glass substrates specifically designed for semiconductor packaging applications and semiconductor manufacturing process support.

Wafer-level packaging (WLP) technology - in which the IC is packaged while still part of the wafer - has made remarkable progress with next-generation semiconductor and MEMS devices. This has resulted in a growing need for glass wafers - in particular, those that can match silicon's coefficient of thermal expansion (CTE), thus eliminating the warping that occurs when attempting to directly laminate silicon and glass wafers whose CTE values differ.

Another target technology for the new substrates is fan-out wafer-level packaging (FOWLP), which enhances standard WLP technology to provide a smaller package footprint with improved thermal and electrical performance. It involves joining materials with different CTEs, including silicon wafers, rewiring layers and resin. As combinations and patterns vary from device to device, glass substrates that can provide the optimal CTE for each element are needed. Also, since the alkaline component of ordinary glass can cause contamination in production processes and devices, alkali-free glass is desirable in certain applications.

The new AGC glass substrates can be provided in rectangular and square shapes, as well as traditional round wafers, with thicknesses ranging from 0.2 to 2mm. The glass products cover a wide range of CTE values from 3ppm/°C up to 12ppm/°C.

Visit the AGC Group at www.agc-group.com