IBM slashes next-gen power

July 20, 2015 // By R. Colin Johnson
First IBM Leapfrogged Intel to 7nm, now it's cut power -- by using a 0.3 supply voltage -- while simultaneously increasing speed at advanced nodes by boosting supply voltage during operations.

Dynamic — and interconnect-boosting harnesses what is ordinarily an adversary to speed — capacitive coupling — to momentarily boost supply voltage during operations for up to three-times faster access to SRAM with a 200 picosecond clock pulse width resulting in only a minuscule increase in power, according to IBM scientist Rajiv Joshi and colleagues at the Watson Research Center in Yorktown, Heights, New York.

"We are offering excellent solutions, which will be needed for future generations. In our work we have shown an excellent scalability through novel circuit techniques and predictive analytics," Joshi told EE Times. "We will attempt to make these circuits even more efficient/cost effective exploiting the future technology beyond 14nm."

All of Joshi's group’s experiments, so far, have been on silicon-on-insulator (SOI) substrates at the 14nm node using immersion lithography. IBM has mastered this in the lab, achieving the lowest reported operating voltage (0.3) for a FinFET, even in the presence of process variability which gets worse when scaling beyond 14nm to 10-and-7nm.

"Process variability, which we call process, voltage and temperature related, is a greater challenge to get to 7-nanometer," Joshi said.

IBM Research (Yorktown Heights, N.Y.) has discovered a way to cut supply voltage to just 0.2 volts, clearing the way to 10-to-7 nanometer at lower power than Intel, according to scientist Rajiv Joshi (pictured above). Source: IBM.

IBM, however, believes that investments in its own unique design methodology tools—including predictive analytics and Technology CAD (TCAD)—has and will continue to allow it to overcome the obstacles to its "boosting" technology beyond the 14nm node, by anticipating problems and solving them before they even crop-up on test chips in the lab.

"Our super-fast predictive failure analytic techniques are state of the art, novel and proven, which will help take us to the 7nm regime by predicting design failures," Joshi said.

The boosting technique is combined with a simultaneous negative boost to bit-lines to improve yield. The