IBM to test wafer pruning

May 27, 2011 // By R. Colin Johnson
A new wafer pruning technique could save 15 percent in semiconductor chip manufacturing costs and increase profits per chip by as much as 12 percent, according to the Semiconductor Research Corp., which funded development of the technique at the University of California at Los Angeles (UCLA).

The new wafer pruning technique is currently being characterized by IBM Corp., for its 45-nanometer process, using on-wafer monitoring structures that can be probed during fabrication to spot bad wafers early-on.

The wafer pruning technique positions the test structures between die on a wafer, similar to the test structures installed there today to monitor process drift. By repurposing these test structures for pruning wafers—that is, rejecting wafers early in their fabrication by detecting errors in the test structures—an overall boost in yields should increase profits, which IBM is currently measuring.

"Wafer pruning ultimately leads to less expensive and higher performing electronics devices, especially if the pruning can be done during the early stages of manufacturing," said Puneet Gupta, an SRC alumni and professor of electrical engineering at UCLA. "Pruning is also especially useful in the early stages of yield ramp for a new chip."

Design dependent process monitoring spots bad wafers early-on by comparing design house timing and power models with measurements made on special test structures between die.

The design-dependent process installs easy-to-test structures which detect anomalies in capacitance, resistance and other telltale signs which indicate that nearby die are probably bad too. If enough errors are detected in early stages of processing a wafer, it can be rejected. By pruning bad wafers, there is a significant saving in the cost of additional processing steps, such as the complex metallization layers that are usually left for last.

Gupta estimates that 70 percent of failed chips can be pruned using test structures to detect a wide range of power level and performance variations. Simple test structures positioned between die enable the spotting of detects early-on, before dicing and packaging, thus reducing the testing cost of detecting faults in finished chips too.

"Design-assisted manufacturing techniques like those developed by professor Gupta, leverage design information to reduce process control requirements, something all our members can benefit from," said Bill Joyner, SRC director