SAR ADCs provide high power efficiencies as well as a small form factor, making this architecture attractive for a wide variety of wireless applications. SAR ADCs are frequently the preferred architecture for applications with moderate resolution and sampling frequencies. However, wireless receivers for next-generation high bandwidth standards such as LTE-advanced and the new generations of Wi-Fi require much faster ADCs.
The new SAR ADC architecture, developed by imec and Renesas Electronics, is an answer to the need for much faster low-power ADCs with small form factor. The reported ADC is an ultra-low power (1.7 mWatt) high resolution (11b) fully-dynamic, two-step interleaved pipelined SAR ADC achieving a record power efficiency of 10fJoule per conversion step at a sampling speed as high as 250MSamples/s. This is a spectacular increase of the speed and sampling frequency, which are both an order of magnitude better than state-of-the art available ADC IP blocks.
The result is obtained with a new converter architecture based on prior groundbreaking ADC designs from imec, exploiting the opportunities of modern advanced CMOS technologies. The design uses completely dynamic circuits, such that the power consumption scales linearly with the sampling frequency, and is implemented with a maximum amount of digital content, leaving the comparator as the only analog building block.
The ADC prototype has been manufactured in 40 nm CMOS with a core chip area of 0.066 mm2. Measurements show a DNL and INL of respectively 0.8/-0.5 and 1.1/-1.5 LSB. The dynamic performance is characterized by 62 dB SNDR (10.0 ENOB) at 10 MSamples/s, which is maintained up to 9.5 ENOB level for a sampling speed of up to 250 MSamples/s. The power consumption is 6.9pJoule per conversion (70 µWatt at 10 MSamples/s, 1.7 mWatt at 250 MSamples/s), resulting in a spectacular energy efficiency of 7 to 10fJoule per conversion-step.
Also at ISSCC, imec and Renesas Electronics is presenting a new way to connect the ADC architecture with the complete radio