Intel tips 22-nm tri-gate, but mobile is MIA

May 05, 2011 // By Mark LaPedus
As expected, Intel Corp., rolled out its 22-nm process—with a twist. The chip giant introduced the process, based on its long-awaited 3-D transistor design, dubbed tri-gate. First disclosed by Intel in 2002, the tri-gate transistor will form the basis of its 22-nm node. Intel also demonstrated the world's first 22-nm microprocessor, codenamed Ivy Bridge.

Ivy Bridge-based Core family processors will be the first high-volume chips to use tri-gate transistors. Ivy Bridge is slated for high-volume production readiness by the end of this year.

But missing from the announcement was a 22-nm mobile processor, which could fend off competitive threats from the ARM camp.

Intel's 22-nm process will also be based on Intel's third-generation high-k/metal-gate scheme. It will also use copper interconnects, strain silicon and other features. Like 32-nm, Intel will make use of 193-nm immersion lithography.

Intel did not disclose any details about the low-k interconnect technology. Intel insists that it will not use silicon-on-insulator (SOI) technology. SOI wafers will add about 10 percent to total process cost, according to Intel.

The tri-gate transistor represents a major shift in the IC industry. For decades, the industry has used the traditional "flat" two-dimensional planar gate. Intel seeks to replace the planar gate with a thin three-dimensional silicon fin that rises up vertically from the silicon substrate.

Other leading-edge chip makers are looking at multi-gate transistor structures, including IBM’s fab club, TSMC, among others. The tri-gate transistor technology is known outside Intel as a FinFET. One company, TSMC, plans to roll out its initial FinFETs at the 14-nm node.

In any case, Intel will have at least a ''three year lead’’ in the multi-gate transistor race, said Mark Bohr, an Intel senior fellow and director of process architecture and integration, at a press event here. Bohr said the tri-gate technology can scale to the 14-nm node, but he stopped short of talking about the next node after 22-nm.

The chip giant calls its technology a ''fully depleted tri-gate transistor. Tri-gate transistors form conducting channels on three sides of a vertical fin structure, providing 'fully depleted’ operation.''

"Control of current is accomplished by implementing a gate on each of the three sides of the fin—two on each side and one across the top—rather than just one on