Singapore's Institute of Microelectronics (IME) has formed two consortia to help with this process and leverage its research expertise in MEMS, photonics and packaging. The first is a consortium of nearly a dozen manufacturers – from InvenSense and Corning to Fraunhofer and NTT – has pledged to meld MEMS and photonics before the end of the decade.
"The Internet of Things will drive sensor growth to trillions of units as sensors become a fundamental economic driver. Disruptive sensor applications are expected to change our lives. Materializing these huge business opportunities requires a paradigm shift in sensor innovation and manufacturing." Mo Maghsoudnia, vice president, technology and worldwide manufacturing at InvenSense told EE Times . "IME's packaging consortia partnership will allow us to identify and develop MEMS packaging innovative solutions in order to scale up for the IoT."
Silicon grating coupler: 2D grating to achieve polarisation diversity performance; Grating coupler with silicon overlay to reduce the coupling loss (<2.6 dB) on 220- nanometer (nm)-thick Silicon on Insulator (SOI). Source: IME.
The Singapore-based Agency for Science, Technology and Research (A*STAR) has commissioned its Institute of Microelectronics (IME) to form two consortia, first the MEMS and Photonics Consortium. So far their ranks include Delta Electronics Inc., InvenSense Inc., Standing Egg Inc., STATS ChipPAC Ltd, ULVAC, Inc. The second consortium is the Silicon Photonics Packaging Consortium consisting of Accelink Technologies Co., Ltd., Corning Inc., Fujikura Ltd., Fraunhofer Heinrich Hertz Institute and NTT.
The Silicon Photonics Packaging Consortium is now entering its second phase (see figures for progress already made in the first stage) but the MEMS consortium is just getting kicked off, pledging to fully integrate heterogeneous MEMS+Photonic devices into the same package using what was originally called the Nasiri Process ( ). The Nasiri Process caps the MEMS chip with its own application specific integrated circuit (ASIC, here containing the silicon photonics) thereby hermetically sealing the stacked die at the wafer scale without requiring