Japanese researchers scale IGBT features for energy savings

December 06, 2016 // By Graham Prophet
Researchers at the Tokyo Institute of Technology have described a route to energy savings in silicon power transistor, through a 3D approach to device feature scaling. Improved efficiency is reported in a low-cost silicon power transistor structure by scaling down in all three dimensions.

While progress in energy efficiencies has been reported with alternative materials such as SiC and GaN, energy-savings in standard inexpensive and widely used silicon devices are still keenly sought, the team observes. K Tsutsui at Tokyo Institute of Technology and colleagues in Japan studied silicon insulated gate bipolar transistors (IGBTs). While the efficiency of IGBTs is good, reducing the on-resistance, or the collector to emitter saturation voltage (Vce(sat)), could help increase the energy efficiency of these devices further.

Previous investigations have highlighted that increases in the “injection enhancement (IE) effect”, which give rise to more charge carriers, leads to a reduction in Vce(sat). Although this has been achieved by reducing the mesa width in the device structure, the mesa resistance was thereby increased as well. Reducing the mesa height could help counter the increased resistance but is prone to impeding the (IE) effect. Instead the researchers reduced the mesa width, gate length, and the oxide thickness in the MOSFET to increase the IE effect and so reduce Vce(sat) from 1.70 to 1.26V. With these alterations the researchers also used a reduced gate voltage, which has advantages for CMOS integration.

They conclude, “It was experimentally confirmed for the first time that significant Vce(sat) reduction can be achieved by scaling the IGBT both in the lateral and vertical dimensions with a decrease in the gate voltage.”