Analog designers have always had to worry about physical layout to get good matching of devices. Variations in doping levels across the chip, usually assumed to be in a gradient in one or two dimensions, could be handled by clever layout such as common centroid devices. The same is true for temperature variations created by on-chip power devices: With currents of 10 A or more on power conversion/regulation devices, thermal gradients become a real issue.
As process geometries reduced, a new type of variability was introduced – collectively known as "layout-dependent effects" or LDE for short.
One example of an LDE is the proximity of devices to the well edges. The distance of devices to a well edge has an effect on the Vt (threshold voltage) of the device. The cause is implant ions scattering off the resist sidewall used to define the well, thus increasing Vt by several to tens of millivolts. (See "Layout-Dependent Proximity Effects in Deep Nanoscale CMOS," John V Faricelli, IEEE CICC 2010.)
How Vt varies with spacing from well edge.