Making design-for-test a push-button process

March 02, 2016 // By Philip Ling
Implementing a Design for Test approach when designing PCBs at the schematic capture stage can now be significantly assisted using an innovative and free software extension that adds design verification to Altium Designer.

The concept of ‘right by design’ could imply that the design in question will always work as expected, so there is no need to test it once it has been designed ‘right’. While this is true, in principle, it is also true that testing isn’t primarily a process of finding design faults; that’s a development issue.

Although there is always the potential for new ‘bugs’ to appear at any time, faults that appear after the design phase is complete, particularly in mature products, are likely to be the introduced by the manufacturing process. The list of potential manufacturing defects that can occur in a wave soldering process, for example, is long and includes: incomplete joints; dry, cracked or bulbous joints; lifted pads or resist; pad contamination; solder balling and, of course, open circuits and solder shorts.

Any of these defects can stop a board from working and some may not become apparent until long after it has been shipped. Adopting a Design for Manufacture (DFM) approach can help minimise the occurrence of these types of defects and these are measures that are normally best applied at the PCB layout stage. Modern design tools can help automate this by imposing design rules during this stage, for example.

Despite how well a board is laid out, manufacturing defects are inevitable and so need to be found before the product is shipped, during the test process. Adopting a Design for Test (DFT) approach can ensure that detecting and locating manufacturing defects is possible, even faults that are located beneath surface mounted devices. Rather than strict design ‘rules’, such as minimum spacing between tracks, or routing on specific layers, DFT involves approaches that need to be more widely adopted earlier, and implemented at the schematic capture stage.

 

DFT, right by design

Designing for test is, perhaps, more subjective than designing for manufacture. What may be right for one design may not be right for another, due to cost, space or complexity constraints. What is almost uniformly agreed amongst IC manufacturers, however, is that including a DFT technology such as Boundary Scan in complex integrated devices is now the norm.

While JTAG is often used to debug software running on a microprocessor, boundary scan has far wider application. It was developed to address the challenge of finding manufacturing defects ‘hidden’ beneath advanced surface mount components (typically Ball Grid Arrays, or BGAs). It offers a level of test access that is significantly greater and more cost-effective than many other forms of test and, perhaps even more significantly, because it is ‘built-in’ to devices it doesn’t impose a premium on the cost of those devices. Most FPGAs/CPLDs and processors (including microcontrollers), as well as some fixed-function parts such as Ethernet transceivers, interface controllers and PCI Express PHYs now implement boundary scan.

Accessing boundary scan functionality in a manufactured product requires the right specialist hardware and software, but ensuring your design is ready to offer that access is free; it simply requires a Design for Test approach at the schematic capture stage of development. Attempting to implement or correct a boundary scan chain during or after PCB layout is effectively futile; making sure it’s right by design during schematic capture is simpler and, therefore, much more cost effective.